臺灣博碩士論文加值系統

　　工作週期校正電路(Duty Cycle Corrector, DCC)現今正廣泛地運用於雙倍資料速度同步動態隨機存取記憶體(DDR SDRAM)、雙取樣類比至數位轉換器(Double-Sampling ADC)、時脈資料回復電路(clock data recovery, CDR)等電路，這些電路由於需仰賴時脈的正負緣對資料進行存取的運作，因此工作週期是否為50%將扮演著重要的角色。另一方面，由於大多數的時脈訊號皆由DLL或PLL產生，但因其工作週期會產生劣化的現象，所以也得運用DCC將其工作週期校正成50%。
　　DCC於設計上可分做兩種不同的架構：數位式(Digital Type)和類比式(Analog Type)，數位式的架構多以非回授(non-feedback)為主，因此其鎖定速度較快，但是準確性則較差；相較之下，類比式的架構則大多採用回授(feedback)的方式，以達到較佳的精確度，但校正鎖定速度則較緩慢。為了擷取雙方的優點，本論文將提出另一種以游標卡尺式原理為基礎的混合回授式架構，達到既可快速鎖定又兼具高精確度的特色。
　　本電路主要有兩項特點：第一，傳統數位式架構之精確度受限於一個延遲單元的延遲時間，本電路將大幅提升其精確度至兩個延遲單元間的時間差值，即遠小於一個延遲單元的延遲時間；第二，傳統類比式架構之鎖定速度較為冗長，本電路理論上僅需10個時脈週期，即可完成校正。
　　此工作週期校正電路以TSMC 0.18um 1P6M製程實現，可校正頻率和工作週期範圍為250MHz~1GHz和40%~60%，校正精確度為-0.86%~+0.51%，晶片面積為0.668 × 0.593 mm2；在800MHz情況下，功率消耗為16.8mW。

The duty cycle corrector (DCC) is widely adopted by DDR (double data rate)-SDRAM, half-rate CDR (clock data recovery), and Double-Sampling ADC. The clock siognlals generated DLL (delay locked loop) and PLL (phase locked loop) usually face with asymmetric duty cycle problems and must be corrected by duty cycle correctors.
According to the literatures, the implemention of DCC can be divided into two catagories: the digital type and the analog type. The digital DCCs adopt non-feedback control to gain faster locking speed at the expense of less accuracy. On the contrary, the analog DCCs utilize feedback control to get better accuracy but longer locking time. To gain the advantages of both types, a mixed-type feedback DCC based on vernier principle is proposed in this thesis to achieve extremely high accuracy. With mixed-type operation, it needs only 10 clock cycles for locking, which is much less than those of the conventional analog versions. Furthermore, the effective resolution of the DCC is made to be the difference of two delay cells and the accuracy is substantially improved from those of the conventional digital ones.
The proposed circuit has been fabricated in a TSMC 0.18-μm CMOS technology. The operation frequency range and duty-cycle correctable range are 250MHz ~ 1GHz and 40% ~ 60% respectively. The measured error is proven to be merely -0.86%~+0.51%. The chip area is 0.668 × 0.593mm2 only and the power consumption is 16.8mW at 800 MHz.

第1章 緒論 1
1-1 研究背景 1
1-2 發展現況與研究動機 6
1-3 論文架構 8
第2章 工作週期校正電路 9
2-1 數位式工作週期校正電路 9
2-2 類比式工作週期校正電路 24
2-3 綜合比較 32
第3章 游標卡尺式之高精度工作週期校正電路 33
3-1 架構簡介 33
3-2 整體電路介紹 37
3-3 游標卡尺式之壓控延遲線(VERNIER VCDL) 39
3-4 全週期掃描電路/時間至數位轉換器 41
3-5 延遲時間控制電路 43
3-6 可調延遲單元之分配電路 44
3-7 準確度與鎖定時間的妥協(TRADE OFF) 46
第4章 電路設計實作與模擬 48
4-1 設計流程 48
4-2 數位與類比電路之分割設計考量 51
4-3 類比電路設計與模擬 52
4-4 數位電路設計與模擬 62
4-5 混合模式電路設計與模擬 72
第5章 晶片佈局與考量 90
5-1 仿效元件(DUMMY) 90
5-2 屏蔽技巧(SHIELDING) 91
5-3 GSG I/O PAD 93
5-4 佈局圖與晶片規劃 93
第6章 晶片量測 96
6-1 量測環境 96
6-2 量測結果 99
第7章 晶片比較與未來展望 102
7-1 晶片效能比較 102
7-2 未來展望 103
參 考 文 獻 104

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