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研究生:嚴吉緯
研究生(外文):Ji-wei Yan
論文名稱:雙PLL核心之高精度數位至時間轉換器
論文名稱(外文):High Accuracy Digital-to-Time Converter with Dual PLLs
指導教授:陳伯奇
指導教授(外文):Poki Chen
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:131
中文關鍵詞:數位至時間轉換器時脈產生器游標卡尺法鎖相迴路
外文關鍵詞:Digital-to-time Convertertime generatorverinerphase-locked loop
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隨著積體電路系統的發展,對各種高解析度之轉換器需求也急速的增加,因此高精度數位至時間轉換器的地位也日漸重要,其最主要應用在許多自動測試儀器及晶片上,迄今已發展出各種不同的架構及電路形式,適用於各項測試機台儀器中。其中,游標卡尺法在追求高解析度上為眾多方法中之翹楚,由於一般數位至時間轉換器利用游標卡尺法來實現之目的係利用兩相近之參考頻率來達成高解析度目標,然而其量測範圍往往無法超過一個參考週期;本研究提出增加量測範圍之電路以解決量測範圍受限之缺點,並提高整體最佳解析度達到8.3ps,最寬脈波產生寬度達到1�酨以上;此外,為有效降低環境變異(PVT)之影響,利用兩組鎖相迴路(Phase-Locked Loop)來自動校準該二參考頻率之振盪週期以達成解析度不受影響之目的。本晶片以TSMC 0.35-um CMOS 2P4M標準製程,輸入操作頻率為1.83MHz,在輸入3.3伏特的工作電壓下,總功率消耗為80毫瓦,全部晶片面積為2.01mm2。
A high accuracy Digital-to-Time Converter (DTC) is proposed in the thesis to fit the dramatically increased demand of nowadays VLSI test chips or advance test systems. Many kinds of DTC have been developed by researchers. Among those, the vernier DTC is the best one in some aspects. Originally, the vernier principle is applied to high resolution DTC by using two reference clock with very close frequencies to make the effective resolution equal to the period difference of the reference clocks. However, the operation range is usually limited to one reference period. The operation range limitation is successfully eliminated in the proposed DTC, and two phase-locked loops are utilized to alleviate the PVT sensitivity to achieve a resolution as fine as 9 ps. The realized operation range is 1�酨 which can be extended to infinity theoretically.
This proposed chip have been implemented in a TSMC 0.35um 2P4M standard CMOS process. The reference clock frequency is designed to be 1.83 MHz, and the power consumption is 80mW under 3.3v single powersupply. The total chip size is 2.01mm2.
第一章 緒論 1
1-1 研究動機 1
1-2 論文架構 3
第二章 數位至時間轉換器 4
2-1 數位至時間轉換器簡介 4
2-2 架構說明 6
2-2.1 絕對時間延遲之數位至時間轉換器 6
2-2.2 相對時間延遲之數位至時間轉換器 9
2-3 本論文架構 13
2-3.1 游標卡尺法之數位至時間轉換器 13
第三章 鎖相迴路原理及設計 18
3-1 各種鎖相迴路型態介紹 19
3-1.1 線性鎖相迴路 (Linear PLL,LPLL) 19
3-1.2 半數位鎖相迴路 (Half-Digital PLL,HDPLL) 20
3-1.3 全數位鎖相迴路 (All-Digital PLL,ADPLL) 22
3-2 鎖相迴路之應用 23
3-2.1 鎖相迴路的倍頻功能 23
3-2.2 減少不對稱的時脈週期 25
3-2.3 減少雜訊和資料的再重建 26
3-3 鎖相迴路各區塊電路說明與討論 28
3-3.1 相位頻率偵測器(Phase / Frequency detector) 28
3-3.2 充電泵(Charge Pump) 34
3-3.3 電壓控制振盪器(Voltage Control Oscillator) 42
3-3.4 除頻器(Frequency Divider) 53
3-3.5 迴路濾波器(Loop Filter)與穩定度分析 58
3-3.5.1 二階鎖相迴路(Second-order PLL) 60
3-3.5.2 三階鎖相迴路(Thrid-order PLL) 62
3-3.5.3 雜訊響應(Noise Response) 67
第四章 鎖相迴路模擬與驗證 71
4-1 設計流程與考量 71
4-2 相位頻率偵測器電路設計與模擬 73
4-3 充電泵電路設計與模擬 75
4-4 壓控震盪器電路設計與模擬 78
4-5 除頻器電路與模擬 84
4-6 迴路濾波器 86
4-7 鎖相迴路整體功能模擬 87
第五章 數位至時間轉換器設計與模擬 94
5-1 加載型下數計數器電路與模擬 94
5-2 數位至時間轉換器電路模擬 99
第六章 實驗結果與未來展望 106
6-1 晶片佈局 106
6-2 量測環境 109
6-3 量測結果 113
6-4 結論與未來展望 115
6-4.1 結論 115
6-4.2 未來展望 115
參 考 文 獻 116
[1] Gasbarro, J.A.; Horowitz, M.A.”Integrated Pin Electionics for VLSI Functional Testers”IEEE J. Solid-State Circuits, Volume 24, Issue2, April 1989 Page(s):331 – 337.
[2] Chapman, J.; Currin, J.; Payne, S”A Low-Cost High-Performance CMOS Timing Vernier forATE” Test Conference Proceedings International, 21-25 Oct. 1995 Page(s):459 – 468
[3] Credence System Corp., “STS 6000 System Description,” 1991
[4] James A.Gasbarro and Mark A.Horowitz, ”Integrated Pin Electronic for VLSI functional testers,” IEEE J. Solid-State Circuits,Vol.24, No.2, pp.331~337, Apr.1989
[5] Jim Chapman, ”High performance CMOS based VLSI testers:timing control andcompensation,” IEEE International Test Conference,pp.59~67,1992
[6] Robbins et al. “Low cost timing generator for automatic test equipment operating at high data rates,” U.S Patent ,No.5566188 Oct.15,1996
[7] S.Katsu , T.Ueda , M.Kazumura ,and G. Kano, “A GaAs programmable timer with 125-ps delay time resolution,” ISSCC Dig.Tech. Papers , pp.16~17, Feb. 1988
[8] Tai-Ichi Otsuji and Naoaki Narumi, ”A 10-ps resolution , process-Insensitive timing generator IC,” IEEE J. Solid-State Circuits ,Vol.24,No.5 ,OCT. 1989
[9] Christopher W .Branson, ”Integrated Pin Electronics for a VLSI test system,” IEEE Trans. on Industrial Electronics, Vol.36 ,No.2, MAY.1989
[10] Motorola,Inc.,”MC10E195”,Motorola semiconductor technical data,1996
[11] Analog Devices datasheet,”AD9501,Digitally programmable delay generator,”
[12] Christiansen, J.; “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE J. Solid–State Circuits, vol. 31,pp.952-957,July 1996
[13] Baronti, F.; Fanucci, L.; Lunardini, D.; Roncella, R.; Saletti, R., “A high-resolution DLL-based digital-to-time converter for DDS applications,” IEEE International Frequency Control Symposium and PDA Exhibition, pp. 649 – 653, May 2002
[14] Otsuji T.-i., “A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI,” IEEE J. Solid–State Circuits, Vol. 28, pp.941-947, Sept.1993
[15] Rahkonen, T.E.; Kostamovaara, J.T.;“The use of stabilized CMOS delay line for the digitization of short time intervals,” IEEE J. Solid-State Circuits, vol. 28, pp. 887–894, Aug.1993
[16] Hajimiri, A.; Limotyrakis, S.; Lee, T.H.;“Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999
[17] Ting-Yuan Wang, Shih-Min Lin, Hen-Wai Tsao, “Multiple Channel Programmable Timing Generators With Single Cyclic Delay Line,” IEEE Transactions on Instrumentation and Measurement , vol. 53, pp.1295-1303, Aug. 2004
[18] Ting-Yuan Wang, Shih-Min Lin, Hen-Wai Tsao, “Multiple Channel Programmable Timing Generators With Single Cyclic Delay Line,” IEEE Transactions on Instrumentation and Measurement , vol. 53, pp.1295-1303, Aug. 2004
[19] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, “A 320MHz, 1.5 mW 1.35 V CMOS PLL for microprocessor clock generation,” IEEE J. Solid–State Circuits, Vol. 31, pp. 1715-1722, Nov. 1996
[20] Rong-Jyi Yang; Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; Shen-Iuan Liu;” A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit,” Solid-State Circuits, IEEE Journal of Volume 41, Issue 6, June 2006 Page(s):1380 – 1390
[21] Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A., “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using over sampling,” IEEE J. Solid–State Circuits, Vol. 33, pp.713–722, May 1998
[22] Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A., “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using over sampling,” IEEE J. Solid–State Circuits, Vol. 33, pp.713–722, May 1998
[23] J. S. Lee, W. K. Jin, D. M. Choi, G. S. Lee, S. Kim, “A Wide Range PLL for 64X Speed CD-ROMs & 10X Speed DVD-ROMs,” IEEE Tran., Vol. 46, pp. 487-493, Aug. 2000
[24] Chapman, J.; Currin, J.; Payne, S”A Low-Cost High-Performance CMOS Timing Vernier for ATE” Test Conference Proceedings International, 21-25 Oct. 1995 Page(s):459 – 468
[25] Behzad Razavi,“Design of Analog CMOS Integrated Circuits” International Edition 2001, McGraw 2001.
[26] 劉深淵,楊清淵”鎖相迴路”2006年11月
[27] Jeng-Rern Yang, “Phase Lock Loop”, Yuan Ze University.
[28] H. Kondoh et al.,”A 1.5V 250 MHz to 3.0V 622MHz Operation CMOS Phase-Locked Loop With Precharge Type Phase-Frequency Detector,” IECE Trans. Electron, vol. E78-C, no.4, pp.381-388,April,1995.
[29] H. Johansson et al.,” A Simple Precharge CMOS Phase Frequency Detector”, IEEE J. Solid–State Circuits, Vol. 33,no.2, pp. 295-299, Feb. 1998.
[30] S. Kim et al.,” A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE J. Solid–State Circuits, Vol. 32,no.5, pp. 691-699, MAY. 1997.
[31] 陳育融 “ A Novel All Digital Phase Locked Loop(ADPLL) with ultra fast frequency lock and high oscillation frequency”, Master Thesis, Tamkang University, 1997.
[32] Randy H.Katz,”Contemparary Logic Design”, Benjamin/Cumming 1994.
[33] Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 691-700, May 1997.
[34] Maneatis, J.G., “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid–State Circuits, pp.1723-1732, Nov. 1996.
[35] Mansuri, M., Liu, D., Yang, C.-K.K., “Fast Frequency Acquisition Phase-Frequency Detectors for GSamples/s Phase-Locked Loops,” IEEE J. Solid–State Circuits, VOL. 37, NO. 10, pp.1331-1334, Oct 2002.
[36] Myeungsu Kim, Kwengmook Lee, Yongil Kwon, Joonhyung Lim, T.J Park,”5-Ghz Frequency Synthesizer With Auto-Calibration Loop,IEEE Radio Frequency Integrated Circuits Symposium.
[37] W. Rhee, “ Design of high-performance CMOS charge pumps in Phase-Locked loops,” ISCAS Circuits and Systems, vol. 2, pp.545-548, 1999
[38] Hong YU,Yasuaki INOUE, Yan HAN,”A new high Speed Low-Voltage Charge Pump for PLL Application”ASIC 2005,ASICON 2005 6th International Conference on Volume 1,24-27 Oct 2005 Page(s):387-390.
[39] Rhee, W., ”Design of high-performance CMOS charge pumps in phase-locked loops,” ISCAS, Vol. 2, pp545-548, June 1999.
[40] Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim, Suki Kim, ”Charge pump with perfect current matching characteristics in phase-locked loops,” IEEE Electronics Letters, Vol. 36, pp.1907-1908, Nov. 2000.
[41] 卓均勇,”採用改良型半速率線性相位偵測器之時脈及資料回復電路”,國立台灣大學電機資訊學院電子工程學研究所碩士論文,民國96年12月
[42] C, Hsiang Hui, L. Jyh Woei, Y. Ching Yuan, L. Shen Iuan, “ A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE J. Solid–State Circuits, vol. 37, pp. 1021-1027, Aug. 2002.
[43] N.M. Nguyen, R.G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuits, vol.27, pp. 810-820, May 1992.
[44] P. Larsson, “Measurement and analysis of PLL jitter caused by digital switching noise,” IEEE J. Solid-State Circuits, vol. 36, pp. 1113–1119, July 2001.
[45] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999.
[46] Rafael J Betancourt-Zamora,Thomas H Lee”CMOS VCOs for Frequensy Synthesis in Wireless Biotelemetry”,Low Power Electronics and Design,1998 International Symposium on 10-12 Aug 1998.
[47] Kuo-Hsing Cheng, Wei-Bin Yang, “A low power, wide operating frequency and high noise immunity half-digital phased-locked loop,” IEEE Asia-Pacific Conf., pp.263-266, Aug. 2002
[48] Kamran Iravani, Gary Miller,”VCOs with very low sensitivity to noise on the power supply” Custom Integrated Circuits Conference 1998,11-14 May 1998 Page(s):515-518.
[49] In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang, “A CMOS self-regulating VCO with low supply sensitivity,” IEEE J. Solid-State Circuits, vol. 39, pp.42-48, Jan. 2004.
[50] Y. Ji-Ren and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, Vol. 24, pp. 62- 67, Feb. 1989
[51] Y. Ji-Ren and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Circuits, Vol. 32, pp. 62- 69, Jan. 1997
[52] J. Yuan, C. Svensson, “High-speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24 , pp. 62 – 70, Feb. 1989
[53] Mark Vesterbacka,”A static CMOS Master-Slave Flip-Flop Experiment”Electronic Circuits and Systems,2000 ICECS 2000,Volume 2,17-20 Dec 2000 page(s):870-873 vol.2
[54] Ching-Yuan Yang; Guang-Kaai Dehng; Shen-Iuan Liu;” High-speed divide-by-4/5 counterfor a dual-modulus prescaler”, Electronics Letters, Volume 33, Issue 20, 25 Sept. 1997 Page(s):1691 – 1692
[55] Shen-luan Liu, “Analysis and Design of Phase-Locked Loops”, Graduate Institute of Electronics Engineering National Taiwan University.
[56] Behzad Razavi , “Monolithic Phase-Locked Loops and Clock Recovery Circuits — Theory and Design”., IEEE Press 1996
[57] F. M. Gardner , “Charge-Pump Phase-Locked Loops,” IEEE Tran. Comm., vol. Com-28,pp 1849-1858, November 1980
[58] Mozhgan Mansuri, ”Low-Power Low-Jitter On-Chip Clock Generation”, Dissertation, University of California Los Angeles, 2003
[59] S. Katsu, T Ueda, M. Kazumura and G. Kano , “A GaAs programmable timer with 125-ps delay time resolution,” IEEE ISSCC, pp.16~17, Feb 1988
[60] Robbins et al. “Low cost timing generator for automatic test equipment operating at high data rates,” U.S Patent ,No.5566188 Oct.15,1996
[61] James A.Gasbarro and Mark A.Horowitz, ”Integrated Pin Electronic for VLSI functional testers,” IEEE J. Solid-State Circuits,Vol.24, No.2, pp.331~337, Apr.1989
[62] T. Okayasu, M. Suda, K. Yamamoto, S. Kantake, S. Sudou and D. Watanabe, “1.83ps - Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications,” IEEE ISSCC, pp. 2122- 2131, Feb 2006
[63] Analog Devices datasheet,”AD9501,Digitally programmable delay generator,”
[64] Jim Chapman, ”High performance CMOS based VLSI testers:timing control and compensation,” IEEE International Test Conference,pp.59~67,199
[65] Jabri,M.A.; Skellern,D.J. “PIAF: efficient IC floor planning” IEEE Expert[see also IEEE Intelligent system and Their Applications]Volume 4,Issue 2, Summer 1989 Page(s):33-45
[66] B. Razavi, “A study of injection pulling and locking in oscillators,” IEEE Custom Integrated Circuits Conf., pp.21-24, Sept. 2003
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