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研究生:王凱民
研究生(外文):Kai-Ming Wang
論文名稱:具高精度自我校準脈衝擴展器之時間至數位轉換器
論文名稱(外文):A Highly Accurate Time-to-Digital Converter Based on Self-Calibrated Pulse Stretcher
指導教授:陳伯奇
指導教授(外文):Poki Chen
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:133
中文關鍵詞:時間至數位轉換器脈衝擴展器雙斜率法
外文關鍵詞:Time-to-Digital Converter(TDC)Pulse StretcherDual Slope
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本論文提出一個無量測範圍限制、具自我校準脈衝擴展器之高精度時間至數位轉換器(Time-to-digital converter,簡稱TDC),希望藉由自動校準的方式,來降低環境溫度變異、製程參數變異以及工作電壓的改變所造成量測上的誤差,大幅提高時間至數位轉換器之準確度。
本電路的解析度高達19.53ps,以TSMC 0.35um 2P4M製程實現,晶片面積不含輸入/輸出墊(I/O Pad)為0.5mm2。利用單擊觸發方式,範圍在0.4ns~11ns且量測間距為400ps的情形下,測得的INL及DNL只有+0.5LSB~-0.5LSB和+0.87LSB~-0.8LSB。而在量測頻率為0.2/sec之情形下,其消耗功率為19.8mW。
A highly accurate time-to-digital converter (TDC) based on self-calibrated pulse stretcher has been presented to own a theoretically unlimited input range. Through self calibration, the inaccuracy caused by process, voltage and temperature variations can be eliminated to enhance the performance of the TDC substantially.
The test chips have been fabricated in a TSMC 0.35-um 2P4M standard digital CMOS process. The resolution of the proposed TDC is measured to be as fine as 19.53ps with a reference clock of 100MHz and the chip area is merely 0.78mm�e0.645mm, excluding the I/O pads. By true single shot measurements, the measured INL and DNL are within +0.5LSB~-0.5LSB and +0.87LSB~-0.8LSB for 0.4ns to 11ns input range from with 400ps steps. The power consumption is 19.8mW at 0.2 samples/s measurement rate.
目 錄

中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 XI

第一章 序論 1
1.1 研究動機 1
1.2 內容編排方式 4

第二章 時間至數位轉換器 5
2.1 時間至數位轉換器簡介 5
2.2 計數器法之時間至數位轉換器 6
2.3 游標卡尺法之時間至數位轉換器 9
2.4 脈衝縮減法之時間至數位轉換器 14
2.4.1 線性脈衝縮減法 14
2.4.2 循環式脈衝縮減法 16
2.4.3 非均質與均質之脈衝縮減延遲線 18
2.5 起始-停止原理之之時間至數位轉換器 20
2.5.1 類比至數位轉換器法 21
2.5.2 雙斜率法(Dual Slope) 24

第三章 具高精度自我校準脈衝擴展器之時間至數位轉換器 26
3.1 脈衝擴展法之時間至數位轉換器 27
3.2 具高精度自我校準脈衝擴展器之時間至數位轉換器 30
3.3 時間至脈衝控制電路 31
3.3.1 時間至脈衝控制電路介紹 31
3.3.2 介穩態 34
3.4 脈衝擴展器(內插器) 37
3.5 具自我校準之脈衝擴展器 41
3.5.1 具自我校準之脈衝擴展器工作原理 41
3.5.2 內插器開關切換之誤差 45
3.5.3 放電電容間之寄生耦合電容 51
3.5.3.1 放電電容間之寄生耦合電容之解決途徑 52
3.5.4 有限的電流源輸出阻抗 53
3.5.5 循序逼近暫存器(SAR) 55
3.5.6 比較器 58
3.5.6.1 比較器之概論 58
3.5.6.2 比較器原理說明 59
3.5.6.3 比較器之架構選擇 63
3.5.7 計數器 66

第四章 電路模擬與晶片佈局 67
4.1 設計流程與考量 67
4.2 具高精度自我校準脈衝擴展器之時間至數位轉換器模擬
與驗證 70
4.2.1 時間至脈衝控制電路模擬 71
4.2.2 循序逼近暫存器(SAR)模擬 73
4.2.3 具自我校準之脈衝擴展器模擬 75
4.2.4 比較器模擬 79
4.2.5 計數器模擬 82
4.2.6 時間至數位轉換器系統模擬 83
4.3 晶片佈局 88

第五章 量测結果 90
5.1 測試環境 90
5.2 量测結果 97

第六章 結論與未來展望 110
6.1 晶片效能比較 110
6.2 未來展望 112

參考文獻 114
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