臺灣博碩士論文加值系統

本論文描述如何設計一個應用於DSRC (Dedicated Short Range Communication)系統的射頻接收機前端電路。本電路採用direct conversion的架構，其中包含了一個單端輸入，cascode架構的低雜訊放大器（LNA；Low Noise Amplifier），一個單端射頻(RF)輸入、雙端中頻(IF)輸出、Gilbert Cell的主動式雙平衡混波器（Mixer），以及一個雙端輸出、LC-tank交互偶合的壓控振盪器（VCO；Voltage Controlled Oscillator）。利用TSMC 0.18um 1P6M RF CMOS的製程，設計出工作在1伏特，應用於DSRC系統的5.8GHz 射頻接收機前端電路晶片。
整個射頻接收機能夠提供24.97dB的conversion gain、3.43dB的雜訊指數(noise figure)、-14.1dBm的P-1dB，以及-6.36dBm的IIP3，工作電壓為1伏特，整體功率消耗為17.6mW，晶片面積為0.781*1.244 mm2。

This thesis describe a 1 voltage 0.18um CMOS 5.8GHz RF front-end for DSRC (Dedicated Short Range Communication) application. This circuit integrated a single-ended low noise amplifier (LNA), a single-ended RF input, differential IF output, Gilbert Cell types mixer, and a LC-tank voltage controlled oscillator (VCO). The receiver has been using the standard TSMC 0.18um 1P6M RF CMOS process, design a 5.8GHz RF front-end receiver chip for DSRC application. The integrated RF receiver chip has 24.9dB conversion gain, noise figure is 3.43dB. The 1dB compression point is -14.1dBm. The third-order intercept point (IIP3) is -6.36dBm. The total power consumption is 17.6mW from 1V power supply. The integrated RF front end receiver chip area is 0.817*1.244 mm2.

Abstract (in Chinese) I
Abstract (in English) II
Acknowledgement (in Chinese) III
List of Figures VIII
List of Tables XI
Chapter 1 Introduction 11
1.1 Motivation 11
1.2 DSRC Concept 12
1.3 Thesis Organization 13
Chapter 2 Receiver Architecture 14
2.1 Introduction 14
2.2 Receiver Architecture 14
2.2.1 Heterodyne Receiver 15
2.2.2 Homodyne Receiver（Zero-IF Receiver） 16
2.3 Receiver Specification 17
2.3.1 Noise Figure 17
2.3.2 Linearity 21
2.3.3 Stability 24
2.3.4 Conversion Gain 24
2.3.5 Leakage 25
2.3.6 Tuning Range 26
Chapter 3 Low Noise Amplifier Implementation 27
3.1 Introduction 27
3.2 Single-End Low Noise Amplifier Design 27
3.2.1 Impedance Matching 29
3.2.2 Capacitor coupling in CS LNA 29
3.2.3 Capacitor for input matching 31
3.2.4 Schematic of proposed LNA 33
3.3 Simulation Results 35
Chapter 4 Voltage Controlled Oscillator Implementation 41
4.1 Introduction 41
4.2 Oscillator Basic 42
4.3 Design of LC Tank VCO 44
4.3.1 Negative-Gm generation with a cross-couple pair 44
4.3.2 Varactor Circuit Architecture 45
4.3.3 Switched Capacitor Array 46
4.3.4 Output Buffer 47
4.3.5 Schematic of Proposed VCO 48
4.4 Simulation Results 51
4.5 Measurement Results 53
4.5.1 Measurement Method and Instrument of the VCO circuit 55
4.5.2 Tuning Range of the VCO circuit 55
4.5.3 Phase Noise and Spectrum of the VCO 58
4.5.4 Microphotograph of the fabricated VCO 59
4.6 Conclusion 62
Chapter 5 Mixer and Front-end Implementation 64
5.1 Introduction 64
5.2 Mixer Concept 64
5.2.1 Mixer Block Diagram 66
5.2.2 The type of Mixer 66
5.3 Signal Balance Mixer and Double Balance Mixer 67
5.3.1 Signal Balance Mixer 67
5.3.2 Double Balance Mixer 68
5.4 Design of Mixer 69
5.5 Simulation Results 71
5.6 Mixer Conclusion 76
5.7 Front End Implementation 77
5.7.1 Design of Front End 77
5.7.2 Simulation Results 78
5.7.3 Measurement Method 85
Chapter 6 Conclusion and Future work 90
6.1 Conclusion 90
6.2 Future work 91
Reference 92

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