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研究生:謝育廷
研究生(外文):Yu-Ting Hsieh
論文名稱:X結構時脈繞線之次最佳化研究
論文名稱(外文):Suboptimality for clock routing in X-architecture
指導教授:陳維美
指導教授(外文):Wei-Mei Chen
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:47
中文關鍵詞:λ-幾何繞線零時脈誤差繞線X-結構
外文關鍵詞:λ-geometry routingzero-skew clock routingX-architecture
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在高效能的VLSI同步電路上,時脈誤差會導致電路工作錯誤,建立一個零時脈誤差的時脈繞線是很重要的議題。DME(Deferred Merge Embedding)是最常見的時脈繞線建立法,它可有效的縮短總線段長。而不同的繞線結構亦可縮短總線段長,因此λ-幾何繞線提供了多種不同的繞線方向,如Manhattan-結構、Y-結構、X-結構及歐幾里得幾何。
本研究整合時脈繞線之設計流程,利用有效的叢集方式分群後,並以DME建立零時脈誤差的時脈繞線,最後用Suboptimize演算法來找出潛在的改進事件,調整中繼點,以此程序可建出總線段長較短的零時脈誤差的時脈繞線總且具有較小的連線延遲。經標準時脈Benchmark實驗後,數據顯示與同為X-architecture的繞線演算法比較,總線段長平均減少了14%;在功率消耗上平均減少了11.07%;在延遲時間上平均減少了28.79%。
In the high performance VLSI synchronous systems, clock skew might cause circuit work fault. To construct zero-skew clock routing is an important issue. The DME (Deferred Merge Embedding) algorithm is a popular method for zero-skew clock routing construction to shorten wirelength efficiently. There are various routing architectures for providing more available directions to reduce wirelength. λ-geometry routing allows new routing orientations, such as Manhattan-architecture, the Y-architecture, the X-architecture, and the Euclidean-geometry.
In this thesis we integrate the design flow of clock routing by utilizing efficient clustering algorithm, applying DME to construct zero-skew clock routing, and using our Suboptimize algorithm to improve the DME placement. The suboptimality can reduce wirelength and delay. The experimental results show that the Suboptimize algorithm achieves 14% reduction of wirelength, 11.07% reduction of power and 28.79% reduction of delay, compared with related X-architecture clock routing algorithms.
中文摘要 i
英文摘要 ii
目錄 iii
表目錄 iv
圖目錄 v

第一章 序論 1
1.1 晶片系統結構簡介 1
1.2 時脈繞線相關背景知識 2
1.2.1 時脈設計方法 2
1.2.2 各種時脈繞線法 3
第二章 延遲模式 8
2.1 Linear延遲模式 8
2.2 Elmore延遲模式 9
2.3 FED延遲模式 13
第三章 時脈繞線法 16
3.1 叢集方式 16
3.1.1 BB(Balance Bi-partition) 16
3.1.2 CL(Clustering-based) 18
3.1 延緩合併嵌入 21
3.1.1 Bottom Up Phase 23
3.1.2 Top Down Phase 26
3.2 次最佳化繞線 28
第四章 實驗結果 35
第五章 結論與未來展望 45
5.1 結論 45
5.2 未來展望 45

參考文獻 46
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