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研究生:王忠偉
研究生(外文):Chung-Wei Wang
論文名稱:基於FPGA之崁入式智慧型監錄裝置
論文名稱(外文):An Intelligent Snooper Embedded System by FPGA Implementation
指導教授:王乃堅
指導教授(外文):Nai-Jian Wang
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:59
中文關鍵詞:智慧型監控嵌入式邊界搜尋智慧型記憶
外文關鍵詞:Intelligent SnooperEmbeddedBoundary Scan
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本篇研究提出了一種裝置-[IS (Intelligent Snooper) Device 智
慧型監錄裝置], 在FPGA (Field-Programmable Gate Array)上實
現。因應FPGA 可模組化的特性,JTAG (Joint Test Action Group) 的
標準介面 IEEE 1149.1, 並加上智慧型記憶(Intelligent Memory)功
能後, 成為可執行自我記錄的監錄裝置, 在任何環境下, 可記錄
出系統損壞之前的狀態, 容易找出造成系統損壞的原因。該
IS(Intelligent Snooper) Device 智慧型監錄器的設計有別於目前業
界 Off-Line 的測試, 運用嵌入式(embedded) 技術, 隨時將積體
電路及相關設計的瑕疵快速有效記錄, 得以發現問題的癥結, 提
升問題偵錯能力的穩定度及更有效的管理與控制。
This thesis presents a new device as IS (Intelligent Snooper) on
FPGA (Filed Programmable Gate Array). The using of modularize
characteristic of FPGA, standard interface of JTAG (Joint Test
Action Group) and Intelligent Memory logic generate a self record
snooper device. This design is different from traditional technology
by off-line testing. It uses embedded technology to dig out and
record issue and symptom of integrated circuit and related design
rapidly. The proposed IS (Intelligent Snooper) improves the
maintainability, efficiency and stability in management and control
while troubleshooting.
第一章 緒論......................................................................................................... 1
1.1 研究背景與動機................................................................. 1
1.2 研究目的與方法................................................................. 4
1.3 論文組織........................................................................... 5
第二章 智慧型監錄裝置之發展環境...................................................................... 6
2.1 MAXII 硬體介紹................................................................ 6
2.2 開發環境之軟體平台及設備................................................ 9
2.2.1 Altera 的QuartusII .................................................. 10
2.2.2 ModelSim ................................................................ 11
2.2.3 Tools ....................................................................... 12
2.3 VHDL 硬體描述語言(Hardware Description Language) ......... 13
第三章 智慧型監錄裝置Boundary Scan 原理與硬體設計.................................. 16
3.1 Boundary Scan 原理........................................................... 16
3.1.1 IEEE 1149.1 邊緣掃描發展歷史................................ 16
V
3.1.2 IEEE 1149.1 邊界掃描架構....................................... 17
3.1.3 IEEE Std. 1149.1 邊界掃描– (State Machine) ............ 18
3.1.4 IEEE Std. 1149.1 邊界掃描– (Patent Generate) .......... 20
3.2 MAXII Open Drain 簡介..................................................... 23
3.2.1 Open Drain Setting by QuartusII ................................ 24
3.2.2 Open Drain Setting by MAXII ................................... 25
3.3 5.0-Voltage PCI-Compliant Tolerance by MAXII ................... 27
3.4 智慧型監錄裝置之硬體電路實現....................................... 29
第四章 智慧型監錄裝置模擬與實作.................................................................... 31
4.1 IS 智慧型監錄裝置系統控制邏輯...................................... 32
4.1.1 系統控制邏輯......................................................... 33
4.1.2 系統控制邏輯流程.................................................. 34
4.1.3 系統控制邏輯模擬與結果......................................... 35
4.2 IS 智慧型監錄裝置JTAG Scan Port ................................... 37
4.2.1 JTAG Scan Port ........................................................ 38
4.2.2 JTAG Scan Port 流程................................................ 39
4.2.3 JTAG Scan Port 模擬與結果...................................... 41
4.3 智慧型監錄裝置JTAG Converter ........................................ 42
4.3.1 JTAG Converter ....................................................... 43
4.3.2 JTAG Converter 流程................................................ 44
4.3.3 JTAG Converter 模擬結果......................................... 46
4.4 智慧型監錄裝置Intelligent Memory ................................... 47
4.4.1 Intelligent Memory ................................................... 48
4.4.2 Intelligent Memory 流程........................................... 49
VI
4.4.3 Intelligent Memory 模擬結果.................................... 51
4.5 整合智慧型監錄裝置......................................................... 52
4.5.1 智慧型監錄裝置驗證結果......................................... 53
第五章 結論與未來展望................................................................................... 55
5.1 結論................................................................................ 55
5.2 未來展望......................................................................... 55
參考文獻................................................................................................................. 56
附錄......................................................................................................................... 58
作者簡介................................................................................................................. 59
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57
[17]SN54BCT8244A, SN74BCT8244A,SCAN TEST DEVICES WITH
OCTAL BUFFERSSCBS042E – FEBRUARY 1990 – REVISED JULY
1996
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boundary-scan interface controller”, Test Symposium Proceedings of
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