跳到主要內容

臺灣博碩士論文加值系統

(44.210.83.132) 您好!臺灣時間:2024/05/25 20:17
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:莊愛爾
研究生(外文):Ai-Erh Chuang
論文名稱:90nm節點MOSFETs之熱載子及偏壓溫度不穩定性效應
論文名稱(外文):Hot-Carrier and Bias Temperature Instability Effects on 90 nm Node MOSFETs
指導教授:黃恆盛黃恆盛引用關係陳雙源陳雙源引用關係
指導教授(外文):Heng-Sheng HuangShuang-Yuan Chen
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:機電整合研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:84
中文關鍵詞:熱載子偏壓溫度不穩定性閘二極體介面狀態氧化層陷入電荷
外文關鍵詞:Hot carrierBTIGated-Diodeinterface stateoxide trapped charge
相關次數:
  • 被引用被引用:0
  • 點閱點閱:329
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
熱載子(hot carrier, HC)效應是個主要的可靠度問題,在早期的研究中,金氧半場效電晶體(MOSFET)的HC最劣化情況是在室溫時之汲極雪崩熱載子(DAHC)模式,然而近幾年的研究指出最劣化情況已從DAHC改變到通道熱載子(CHC)模式,且溫度方面已從低溫變化到高溫。另外,近年來隨著閘極氧化層厚度的緊縮,負偏壓溫度不穩定性(NBTI)影響正通道MOSFETs劣化的問題,變的更加嚴重,因此理解這些可靠度問題的嚴重程度是非常重要的。
本研究採用聯華電子公司(UMC)所提供之90奈米製程晶片,實驗分為兩部分,第一部份探討在不同氧化層厚度下,pMOSFET的NBTI效應;第二部份探討n及pMOSFET的HC及BTI效應,研究測試元件的最劣化條件。
藉由I-V及閘極二極體(gated-diode)的量測,第一部份的實驗發現,對具31 Å SiON介電層,在25℃時,氧化層陷入電荷( oxide trapped charges, Not)為主要NBTI之劣化機制,而高溫時,劣化機制轉變成以產生介面狀態電荷(interface-state charges, Nit) 為主;而對具68 Å SiON介電層之pMOSFET言,室溫時,由Not主導NBTI劣化機制,但在高溫時卻是由Nit和Not主導。推測對16 Å SiON之pMOSFET,其劣化機制應與31 Å SiON之pMOSFET相同。有關第二部份最劣化條件的問題,經由多次實驗,對奈米級n及pMOSFET的加壓測試,最劣化條件為在高溫下的CHC模式。對pMOSFETs言,實驗也顯示NBTI的劣化較DAHC來的嚴重,由壽命公式推估,對較薄介電層之電晶體,其NBTI所造成pMOSFET的劣化也愈來愈嚴重。
Hot carrier (HC) effect is a critical reliability problem. In early researches, HC of MOSFET showed the worst degradation at DAHC mode low temperature. However, a recent study reported that the worst case has switched from DAHC to CHC mode from low to high temperature. Furthermore, In recent years, NBTI induced pMOSFET’s degradation has become more serious as oxide thickness keeps thinning. Therefore, it is important to under the degrees of severity of there reliability issues.
In this research, from 90 nm node wafers from United Micro-electronics Corporation (UMC) were used to explore these reliability issues. Two types of experiments were conducted in this work. The first one is to investigate the NBTI effects of pMOSFETs using different oxide thicknesses. The other one is to determine n- and pMOSFETs the worst case between HC and BTI effect.
By I-V and gated diode measurements, the experiments of the first part reveal, that for 31 Å SiON dielectric at 25℃, oxide trapped charges (Not) dominate the NBTI degradation mechanism. However, at high temperature, the NBTI degradation mechanism switches to the generation of interface-state charges (Nit). For 68 Å SiON dielectric, the Not also dominate the NBTI degradation mechanism at room temperature, but Nit and Not determinate the NBTI degradation mechanism at high temperature. It is measurable that pMOSFETs of 16 Å SiON dielectric, also possess similar degradation mechanism as 31 Å SiON dielectric. In the part two of the worst case question, through many experiments of stressing, the nano n- and pMOSFETs, the worst case is found to be CHC mode at high temperature. For pMOSFETs, the NBTI stress exhibits more degradation than DAHC stress. Estimated by the lifetime formula, NBTI induced pMOSFETs degradation will become more serious as more and more thinner dielectric is used.
CONTENTS

ABSTRACT (Chinese)............................................................................................i
ABSTRACT (English)............................................................................................ii
ACKNOWLEDGEMENTS...................................................................................iv
CONTENTS...........................................................................................................v
LIST OF TABLES...............................................................................................viii
LIST OF FIGURES...............................................................................................ix

Chapter 1 Introduction
1.1 Background...................................................................................................1
1.2 Thesis Organization........................................................................................1

Chapter 2 Basic about MOSFET with their HC and NBTI Reliability
2.1 Research Hot Carrier Effect..........................................................................3
2.1.1 Hot Carrier Effect.................................................................................3
2.1.2 Mechanisms..........................................................................................5
2.1.3 Temperature Effect.............................................................................11
2.2 Research NBTI Effect.................................................................................13
2.2.1 NBTI Effect........................................................................................13
2.2.2 Mechanisms……................................................................................16
2.2.3 Temperature Effect.............................................................................19
2.3 The Worst Case Issue under HC and BTI....................................................20
Chapter 3 Experiments designs of HC and BTI
3.1 Experiment Structures.................................................................................27
3.2 Stress Methods............................................................................................28
3.3 Stress and Measurement Conditions............................................................30

Chapter 4 Results and Discussion
4.1. NBTI Effect under Triple Gate Oxide Device Degradation at Elevated Temperature on pMOSFETs......................................................................34
4.1.1 Vt,lin Shift for 10/10 μm (W/L) Devices..............................................34
4.1.2 Id,lin Degradation for 10/10 μm (W/L) Devices...................................36
4.1.3 Id,sat Degradation for 10/10 μm (W/L) Devices...................................39
4.1.4 Gated-Diode Principle and Measurements..........................................41
4.1.4.1 Shockley-Read-Hall Theory of Recombination.........................41
4.1.4.2 Gated-Diode Principle..............................................................42
4.1.4.3 Measurements of 31 Å Devices................................................45
4.1.4.4 Measurements of 68 Å Devices................................................49
4.1.5 Lifetime Model and Prediction.............................................................53
4.2. The Worst Case Issue HC and BTI.............................................................60
4.2.1 Device Degradation at Elevated Temperatures for 10/0.09 μm(W/L) Devices….............................................................................................60
4.2.1.1 nMOSFETs Devices Degradation.............................................60
4.2.1.1.1 Vt,lin Shift for 10/0.09 μm(W/L) Devices.....................60
4.2.1.1.2 Id Degradation for 10/0.09 μm(W/L) Devices..............61
4.2.1.1.3 Id,sat Degradation for 10/0.09 μm(W/L) Devices..........62
4.2.1.2 pMOSFETs Devices Degradation ............................................64
4.2.1.2.1 Vt,lin Shift for 10/0.09 μm(W/L) Devices.....................64
4.2.1.2.2 Id Degradation for 10/0.09 μm(W/L) Devices..............65
4.2.1.2.3 Id,sat Degradation for 10/0.09 μm(W/L) Devices..........66
4.2.1.3 Lifetime Model and Prediction.................................................68

Chapter 5 Conclusions and Future Works
5.1 Conclusions.................................................................................................79
5.2 Future Works...............................................................................................79
References.........................................................................................................81
[1.1]M. Song, P. MacWilliams, and C. S. Woo,“Comparison of NMOS and PMOS hot carrier effect from 300K to 77K,”IEEE Trans Electron Devices, vol. 44, NO. 2, pp.268-275, 1997.
[1.2]S. Y. Chen, C. H. Tu, J. C. Lin, P. W. Kao, W. C. Lin, Z. W. Jhou, S. Chou, J. Ko, and H. S. Haung,“Temperature effect on the hot-carrier induced degradation of PMOSFETs,”IIRW Final Report, 2006, pp. 163-166.
[2.1]A. Schwerin, W. Hansch, and W. Weber,“The relationship between oxide charge and device degradation: A comparative study of n- and p-Channel MOSFET’s.” IEEE Trans. Electron Devices, vol. 12, Dec. 1987.
[2.2]W. Shockley,“Problems related to p-n junction in silicon,”Solid-State electron, Vol. 2, 1961, pp. 35-67.
[2.3]S. Tam, P. K. Ko, and C. Hu,“Lucky-electron model of channel hot electron injection in MOSFET’s,”IEEE Trans. Electron Devices, Sept 1984, pp. 1116-1125.
[2.4]C. Hu, S.C. Tam, F.C. Hsu, P. K. Ko, T. Y. Chen, and K. W. Terrill,“Hot-electron-induced MOSFET degradation-model, monitor, and improvement,”IEEE Trans. Electron Devices, vol. ED-32, Feb. 1985, pp. 375-385.
[2.5]Renesas Technology Crop,“Semiconductor Reliability Handbook,”2006, pp.110.
[2.6]Y.Leblebibi and S. M. Kang,Hot-carrier reliability of MOS VLSI circuits, Kluwer, 1993, pp. 64.
[2.7]S. Wolf,“Silicon processing for the VLSI era,”vol.3-The submicron MOSFET, Ch.7, Thin gate oxides-growth and reliability, 1995, Lattice press.
[2.8]E. Takeda, C. Y. Yang and A. Miura-Hamada,“Hot-carrier effects in MOS devices,”Academic Press, 1995.
[2.9]S. Y. Chen, C. H. Tu, J. C. Lin, P. W. Kao, W. C. Lin, Z. W. Jhou, S. Chou, J. Ko, and H. S. Haung,“Temperature effect on the hot-carrier induced degradation of PMOSFETs,”IIRW Final Report, 2006, pp. 163-166.
[2.10]D. K. Schroder, Jeff A. Babcock,“Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing,”Journal of Applied Physics, Vol. 94, Num. 1, 1 July 2003.
[2.11]B. Deal, M. Sklar, A. S. Grove, and E.H. Show, J. Electronchem. Soc., 114,226 (1967)
[2.12]S. Ogawa, M. Shimaya, and N. Shiono,“Interface-trap generation at ultra-thin SiO2 (4-6nm) Si interface during Negative-Bias Temperature aging,”J.Appl.Phys, vol. 77, 1995, pp.1137-1148.
[2.13]C. Parth asarathy,“Design in Reliability with Emphasis on NBTI,”IEEE Integrated Reliability Workshop (IRW), 2005.
[2.14]N. K. Jha, and V. R. Rao,“A New Oxide Trap-Assisted NBTI Degradation Model,”IEEE Electron Device Lletters, vol.26, No.9, Sep. 2005, pp. 687-689.
[2.15]S. Mahapatra, S. Sharma, P. Bharath Kumar, D. Varghese and D. Saha,“Explanation of Negative Bias Temperature Instability Mechanism in pMOSFETs by Reaction-Diffusion Model,”Extended abstracts of the 2005 International Conference on Solid State Devices and Materials, 2005, pp. 870-871.
[2.16]M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, M. Bidaud, G. Ribes, D. Bargeh,L. Vishnubhotla, B. Tavel, Y. Rey-Tauriac, F. Perrier, N. Revil, F. Arnaud, P. Stolk,“ New hole trapping characterization during NBTI in 65nm node technology nitridation processing,”IEEE, 2004 IRW Final Report, 2004, pp.121-124.
[2.17]M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, N. Revil, and A. Bravaix,“Interface Trap Generation and Hole Trapping Under NBTI and PBTI in Advanced CMOS Technology with a 2-nm Gate Oxide,”IEEE Transaction on device and materials reliability, vol. 4, No. 4, pp. 715-722, Dec. 2004.
[2.18]T. Yang, C. Shen, M. F. Li, C. H. Ang, C. X. Zhu, Y.-C. Yeo, G. Samudra, and D.-L. Kwong,“Interface trap passivation effect in NBTI measurement for pMOSFET with SiON dielectric,”IEEE Electron Device Letters, vol. 26, No. 10, Oct. 2005.
[2.19]T. Yang, C. Shen, M. F. Li, C. H. Ang, C. X. Zhu, Y.-C. Yeo, G. Samudra, Subhash C. Rustagi, M. B. Yu, and D.-L. Kwong,“Fast DNBTI components in p-MOSFET with SiON dielectric,”IEEE Electron Device Letters, vol. 26, No. 11, Nov. 2005.
[2.20]江婉如,NBTI對具有超薄介電層之深次微米P型通道電晶體特性影響之研究,交大電子所碩士論文(黃調元、林鴻志指導),2003.
[2.21]歐育森,金氧半場效電晶體之熱載子與負偏壓溫度效應之探討,成大微電子所碩士論文(陳志芳指導),2003.
[2.22]N. Koike and K. Tatsuuma,“A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs,”IEEE Trans. Device and Materials Reliability, vol. 4, pp.457-466, 2004.
[2.23]S. G. Lee and J. M. Hwang, “Experimental Evidence for Nonlucky Electron Model Effect in 0.15-μm NMOSFETs,”IEEE Tran, vol. 49, 2002, pp.1876-1881.
[2.24]K.Xiu and M. Ketchen, Proc. Electornic Components and Technology Conf, Las Vegas, NV, 2004, pp. 918-923.
[2.25]E, Li, E. Rosenbaum, L. F. Register, J. Tao and Fang,“Hot Carrier Induced Degradation in Deep Submicron MOSFETs at 100°C,”IRPS, pp.103-106,2000.
[2.26]Z. W. Jhou. “DC Hot Carrier Reliability at Elevated Temperatures for nMOSFETs Using 0.13μm Technology,”National Taipei University of Technology Master thesis, July, 2005.
[2.27]T. Hori, Gate Dielectrics and MOS ULSIs, Springers, 1997.
[2.28]C. Guerin, V.Huard, A.Bravaix, M. Denais, J.M. Roux, F. Perrier and W. Baks, “Combined effect of NBTI and Channel Hot Carrier effects in pMOSFETs,” IRE Final Report. Oct. 2005.
[2.29]P. Chaparala, J. Shibley and P. Lim,“Threshold Voltage Drift in pMOSFETS due to NBTI and HCI,”IRW Final Report, pp. 95-97, Oct. 2000.
[3.1]S. Y. Chen, C. H. Tu, J. C. Lin, P. W. Kao, W. C. Lin, Z. W. Jhou, S. Chou, J. Ko, and H. S. Haung,“Temperature effect on the hot-carrier induced degradation of PMOSFETs,”IIRW Final Report, 2006, pp. 163-166.
[4.1]D. A. Neamen, Semiconductor Physics & Devices, 3rd ed. McGraw-Hill; 2003, p.248
[4.2]F. C. Chiu ,W. C. Shih, J. Y. Lee and H. L. Hwang,“An investigation of surface state capture cross-sections for metal-oxide-semiconductor field-effect transistors using HfO2 gate dielectrics,”Microelectronics Reliability , vol. 47, Issues 4-5, April-May 2007, pp. 548-551.
[4.3]S. Chakravarthi, A.T. Krishnan, V. Reddy, C.F. Machala and S. Krishnan,“A comprehensive framework for predictive modeling of negative bias temperature instability,”IRPS, pp. 273-282, 2004.
[4.4]S. Y. Chen, C. H. Tu, J. C. Lin, P. W. Kao, W. C. Lin, Z. W. Jhou, S. Chou, J. Ko, and H. S. Haung,“Temperature effect on the hot-carrier induced degradation of PMOSFETs,”IIRW Final Report, 2006, pp. 163-166.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊