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研究生:江志豪
研究生(外文):Chih-Hao Chiang
論文名稱:90 nm節點窄寬度nMOSFETs於升溫下之HC與PBTI可靠度探討
論文名稱(外文):HC and PBTI Reliability on Narrow Width 90 nm Node nMOSFETs at Elevated Temperatures
指導教授:陳雙源陳雙源引用關係黃恆盛黃恆盛引用關係
指導教授(外文):Shuang-Yuan ChenHeng-Sheng Huang
口試委員:王木俊劉傳璽
口試委員(外文):Mu-Chun WangChuan-Hsi Liu
口試日期:2008-01-23
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:機電整合研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:109
中文關鍵詞:溫度可靠度介面狀態閘二極體量測正偏壓溫度不穩定性熱載子窄寬度
外文關鍵詞:TemperatureReliabilityInterface StateGated Diode MeasurementPBTIHot CarrierNarrow Width
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在現今CMOS技術中,淺溝槽絕緣(STI)不可避免地使用於相鄰電晶體間的絕緣,但其對熱載子(HC)與正偏壓溫度不穩定性(PBTI)等可靠度的影響,至今仍非常不確定,特別是窄寬度的nMOSFET。
在本研究中,採用聯華電子公司所提供之90 nm節點晶片,且以閘極氧化層厚度為31Å與68Å之nMOSFET為目標。對通道長度/寬度(W/L)=10/0.2與0.22/0.2 um的元件,進行通道熱載子(CHC)與汲極雪崩熱載子(DAHC)加壓測試;對W/L=10/10 um與W/L=0.4/10 um的元件,進行PBTI加壓測試。所有測試皆分別以25℃、75℃與125℃三個溫度進行。在加壓測試後,以閘二極體量測法(gated diode method)分析元件電性。由CHC與DAHC的實驗結果得知,與寬通道元件比較,窄通道nMOSFET所產生之介面狀態(interface state)較多,而使其電晶體性能加速退化。推論於CHC加壓測試後,介面狀態主要在STI邊緣與通道區域產生,而造成嚴重地臨界電壓漂移與汲極電流退化。然而,DAHC加壓測試後,推測只於STI邊緣處產生介面狀態。此外,由PBTI實驗結果得知,隨著溫度與電場的增加,寬通道元件參數漂移略大於窄通道元件,此與HC的情況恰好相反,推測主要原因是當電子因垂直電場注入氧化層時,除規矩分佈外,與HC相較,其有較多比例之陷入電荷分佈於STI的側緣,故窄通道元件之PBTI劣化略小於寬通道。
Shallow trench isolation (STI) is inevitable to be used in isolating the neighboring transistors in today CMOS technology, but their influences on hot-carrier (HC) and positive bias temperature instability (PBTI) reliability is not clear especially on the narrow width nMOSFETs.
In this work, nMOSFETs on wafers from 90 nm node of UMC (United Microelectronics Corporation) were characterized, and those with 31Å and 68Å gate oxide thickness were targeted. The devices with channel width/length (W/L) equal to 10/0.2 um and 0.22/0.2 um were stressed under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) conditions. Other devices with W/L equal to 10/10 um and 0.4/10 um were stressed under PBTI conditions. All tests were conducted at temperatures of 25, 75 and 125 ℃. After stresses, gated diode method was used to analyze electrical characteristics of these devices. The CHC and DAHC test results show that the degradation of the narrow width nMOSFETs was enhanced by the generations of interface states. We infer that CHC stresses produce interface states both on STI edges and channel region, causing threshold voltage shifts and drain current degradation seriously. However, we infer that DAHC stresses have only produced interface states on STI edges. In addition, from the experimental results of PBTI, the parameter shifts in wide width devices were slightly larger than narrow width devices as the temperature and electric field increased. The results were opposite to HC stresses. The main presumable reason is, when electrons were injected into the oxide by vertical electric field, the trapped electrons were uniformly located in the channel region and STI sidewalls. This distribution can be attributed to the reason explaining why, contradictory to HC, PBTI has caused the degradation of narrow width devices slightly small than wide width devices.
Contents
Abstract(Chinese)…………………………………………………………………i
Abstract(English)…………………………………………………………………ii
Acknowledgement…………………………………………………………………iv
Contents………………………………………………………………………………v
List of Tables………………………………………………………………………vii
List of Figures………………………………………………………………………viii
Chapter 1 Introduction………………………………………………………………1
1.1 Motivation………………………………………………………………………1
1.2 Thesis Organization……………………………………………………………2
Chapter 2 Basic about MOSFET and HC reliability………………………………3
2.1 MOSFET Device………………………………………………………………3
2.2 Research about Hot Carrier Effect………………………………………………4
2.2.1 Hot Carrier Effect……………………………………………………4
2.2.2 Mechanisms…………………………………………………………6
2.3 Narrow Width Effect and Reverse Narrow Width Effect………………………11
Chapter 3 Experiment designs of HC and PBTI reliability………………………15
3.1 Experimental Structures………………………………………………………15
3.2 Stress Methods…………………………………………………………………15
3.3 Device Fabrication and Split Table……………………………………………17
3.4 Transition Point and Reverse Temperature Effect………………………………18
3.5 Stress Conditions and Parameter Measurements………………………………25
Chapter 4 Results and Discussion of HC…………………………………………28
4.1 Basic Vt and I-V Characteristics for nMOSFET Devices………………………28
4.2 Device Degradation at Elevated Temperatures for nMOSFET Devices………31
4.2.1 CHC and DAHC Stress for nMOSFET Devices……………………31
4.2.2 Vt,lin Shift for nMOSFET Devices under DAHC Stress Mode………36
4.2.3 Vt,lin Shift for nMOSFET Devices under CHC Stress Mode…………38
4.2.4 Id,sat Degradation for nMOSFET Devices under CHC Stress Mode…40
4.2.5 Id,sat Degradation for nMOSFET Devices under DAHC Stress Mode…43

4.3 Gated-Diode Measurements……………………………………………………51
4.3.1 Shockley-Read-Hall Theory of Recombination………………………51
4.3.2 Gated-Diode Principle and Measurements……………………………52
Chapter 5 Results and Discussion of PBTI………………………………………64
5.1 PBTI Experimental Method……………………………………………………64
5.2 PBTI Experimental Results and Disscussion…………………………………65
5.2.1 PBTI Stress for nMOSFET Devices…………………………………65
5.2.2 Vt,lin Shift for nMOSFET Devices under PBTI Stress Mode…………72
5.2.3 Id,sat Degradation for nMOSFET Devices under PBTI Stress Mode…74
5.2.4 Gated-Diode Measurements…………………………………………76
Chapter 6 Conclusions and Future Works………………………………………105
6.1 Conclusions…………………………………………………………………105
6.2 Future Works…………………………………………………………………106
References…………………………………………………………………………107


List of Tables

Table 2.1 Effect Vt factors of different isolation structure…………………………………14
Table 3.1 Split table of experiments……………………………………………………………18
Table 3.2 The measurement conditions………………………………………………26
Table 3.3 The stress conditions for nMOSFETs………………………………………27




































List of Figures

Fig. 2-1 Three dimensions view of basic nMOSFET structure…………………………3
Fig. 2-2 MOS device biased under a high electric field………………………………5
Fig. 2-3 IV characteristics of nMOSFETs device………………………………………6
Fig. 2-4 Energy band about hot carrier tunneling………………………………………7
Fig. 2-5 Major mechanisms of channel hot carrier generation…………………………7
Fig. 2-6 The simulated electric field distribution along the channel in nMOSFETs……8
Fig. 2-7 The schematic gate current behavior (Ig-Vg) in nMOSFET…………………9
Fig. 2-8 Major mechanisms of drain avalanche hot carrier generation………………9
Fig. 2-9 Mechanism about interface trap generation…………………………………10
Fig. 2-10 LDD Structure……………………………………………………………11
Fig. 2-11 Three types of device structures and associated inversion-depletion layer…12
Fig. 2-12 Variation of threshold voltage with gate width for uniform doping…………13
Fig. 2-13 Variation of threshold voltage with gate width in the case of trench isolated buried channel pMOSFET showing the anomalous behavior……………14
Fig. 3-1 Current-time characteristic for 6.5 nm MOS capacitor recorded during a CVS in gate injection mode with Vg = 9 V………………………………………16
Fig. 3-2 Cross-section SEM of shallow trench isolation……………………………17
Fig. 3-3 Experimental substrate currents of wide width device vs. gate voltage………19
Fig. 3-4 Experimental substrate currents of wide width device vs. gate voltage………19
Fig. 3-5 Experimental substrate currents of wide width device vs. gate voltage………20
Fig. 3-6 Experimental substrate currents of wide width device vs. gate voltage………20
Fig. 3-7 Experimental substrate currents of wide width device vs. gate voltage………21
Fig. 3-8 Experimental substrate currents of wide width device vs. gate voltage………21
Fig. 3-9 Experimental substrate currents of wide width device vs. gate voltage………22
Fig. 3-10 Experimental substrate currents of narrow width device vs. gate voltage…23
Fig. 3-11 Experimental substrate currents of narrow width device vs. gate voltage…23
Fig. 3-12 Experimental substrate currents of narrow width device vs. gate voltage…24
Fig. 3-13 Experimental substrate currents of narrow width device vs. gate voltage…24
Fig. 3-14 Experimental substrate currents of narrow width device vs. gate voltage…25
Fig. 3-15 Experimental substrate currents of wide width device vs. gate voltage……26
Fig. 3-16 Experimental substrate currents of narrow width device vs. gate voltage…27
Fig. 4-1 Experimental linear threshold voltage versus channel width for nMOSFETs with triple gate oxide……………………………………...…………………28
Fig. 4-2 Linear threshold voltage versus channel width of nMOSFETs devices………29
Fig. 4-3 Drain currents per width versus gate voltage of nMOSFETs devices………30
Fig. 4-4 Drain currents per width versus drain voltage of nMOSFETs devices………30
Fig. 4-5 Id,lin vs. gate voltage after the CHC stress for wide width nMOSFET………31
Fig. 4-6 Id,lin vs. gate voltage after the CHC stress for narrow width nMOSFET……32
Fig. 4-7 Id,lin vs. gate voltage after the DAHC stress for wide width nMOSFET………32
Fig. 4-8 Id,lin vs. gate voltage after the DAHC stress for narrow width nMOSFET……33
Fig. 4-9 Id,sat vs. drain voltage after the CHC stress for wide width nMOSFET………34
Fig. 4-10 Id,sat vs. drain voltage after the CHC stress for narrow width nMOSFET…34
Fig. 4-11 Id,sat vs. drain voltage after the DAHC stress for wide width nMOSFET……35
Fig. 4-12 Id,sat vs. drain voltage after the DAHC stress for narrow width nMOSFET…35
Fig. 4-13 Vt,lin shifts versus stress time at 25 °C of wide and narrow width devices…36
Fig. 4-14 Vt,lin shifts versus stress time at 75 °C of wide and narrow width devices…37
Fig. 4-15 Vt,lin shifts versus stress time at 125 °C of wide and narrow width devices…37
Fig. 4-16 Vt,lin shifts versus stress time at 25 °C of wide and narrow width devices…38
Fig. 4-17 Vt,lin shifts versus stress time at 75 °C of wide and narrow width devices…39
Fig. 4-18 Vt,lin shifts versus stress time at 125 °C of wide and narrow width devices…39
Fig. 4-19 △Id,sat versus stress time at 25 °C of wide and narrow width devices………40
Fig. 4-20 △Id,sat versus stress time at 75 °C of wide and narrow width devices………41
Fig. 4-21 △Id,sat versus stress time at 125 °C of wide and narrow width devices……41
Fig. 4-22 △Id,sat versus temperatures at Vd=3V after CHC stress 3000 seconds………42
Fig. 4-23 △Id,sat versus stress time at 25 °C of wide and narrow width devices………43
Fig. 4-24 △Id,sat versus stress time at 75 °C of wide and narrow width devices………44
Fig. 4-25 △Id,sat versus stress time at 125 °C of wide and narrow width devices……44
Fig. 4-26 △Id,sat versus temperatures at Vd=3V after DAHC stress 3000 seconds……45
Fig. 4-27 Drain currents vs. drain voltage of wide width device after CHC stress……46
Fig. 4-28 Drain currents vs. drain voltage of narrow width device after CHC stress…46
Fig. 4-29 Drain currents vs. drain voltage of narrow width device after DAHC
stress……………………………………………………………………47
Fig. 4-30 Drain currents vs. drain voltage of narrow width device after DAHC
stress……………………………………………………………………47
Fig. 4-31 ID/W vs. drain voltage of wide and narrow width devices after CHC
stress……………………………………………………………………48
Fig. 4-32 ID/W vs. drain voltage of wide and narrow width devices after DAHC
stress……………………………………………………………………48
Fig. 4-33 Drain currents vs. gate voltage of wide width device after CHC stress……49
Fig. 4-34 Drain currents vs. gate voltage of narrow width device after CHC stress…49
Fig. 4-35 ID/W vs. drain voltage of wide and narrow width devices after CHC
stress……………………………………………………………………50
Fig. 4-36 The four basic trapping and emission processes for the case of an
acceptor-type trap………………………………………………………51
Fig. 4-37 The reverse current IR of the gated diode at various gate voltages…………52
Fig. 4-38. Gated-diode in accumulation………………………………………………53
Fig. 4-39. Gated-diode in depletion…………………………………………………53
Fig. 4-40. Gated-diode in inversion…………………………………………………54
Fig. 4-41. The R-G currents vs. gate voltage of wide width device after CHC stress…55
Fig. 4-42. The R-G currents vs. gate voltage of narrow width device after CHC
stress……………………………………………………………………56
Fig. 4-43. The R-G currents vs. gate voltage of wide width device after DAHC
stress……………………………………………………………………56
Fig. 4-44. The R-G currents vs. gate voltage of narrow width device after DAHC
stress……………………………………………………………………57
Fig. 4-45. The R-G currents vs. gate voltage of wide width device after CHC stress…57
Fig. 4-46. The R-G currents vs. gate voltage of narrow width device after CHC
stress……………………………………………………………………58
Fig. 4-47. The R-G currents vs. gate voltage of wide width device after DAHC
stress……………………………………………………………………58
Fig. 4-48. The R-G currents vs. gate voltage of narrow width device after DAHC
stress……………………………………………………………………59
Fig. 4-49. The R-G currents vs. gate voltage of wide width device after CHC stress…59
Fig. 4-50. The R-G currents vs. gate voltage of narrow width device after CHC
stress……………………………………………………………………60
Fig. 4-51. The R-G currents vs. gate voltage of wide width device after DAHC
stress……………………………………………………………………60
Fig. 4-52. The R-G currents vs. gate voltage of narrow width device after DAHC
stress……………………………………………………………………61
Fig. 4-53. △Igen,s/W vs. temperatures of wide and narrow width devices after stress…62
Fig. 4-54. △Igen,s/W vs. temperatures of wide and narrow width devices after stress…62
Fig. 4-55. △Igen,MJ/W vs. temperatures of wide and narrow width devices after
stress……………………………………………………………………63
Fig. 4-56. △Igen,MJ/W vs. temperatures of wide and narrow width devices after
stress……………………………………………………………………63
Fig. 5-1. Experimental method of positive bias temperature instability……………64
Fig. 5-2. Id,lin vs. gate voltage after the PBTI stress for wide width nMOSFET………65
Fig. 5-3. Id,lin vs. gate voltage after the PBTI stress for wide width nMOSFET………66
Fig. 5-4. Id,lin vs. gate voltage after the PBTI stress for wide width nMOSFET………66
Fig. 5-5. Id,lin vs. gate voltage after the PBTI stress for narrow width nMOSFET……67
Fig. 5-6. Id,lin vs. gate voltage after the PBTI stress for narrow width nMOSFET……67
Fig. 5-7. Id,lin vs. gate voltage after the PBTI stress for narrow width nMOSFET……68
Fig. 5-8. Id,sat vs. drain voltage after the PBTI stress for wide width nMOSFET……69
Fig. 5-9. Id,sat vs. drain voltage after the PBTI stress for wide width nMOSFET……69
Fig. 5-10. Id,sat vs. drain voltage after the PBTI stress for wide width nMOSFET……70
Fig. 5-11. Id,sat vs. drain voltage after the PBTI stress for narrow width nMOSFET…70
Fig. 5-12. Id,sat vs. drain voltage after the PBTI stress for narrow width nMOSFET…71
Fig. 5-13. Id,sat vs. drain voltage after the PBTI stress for narrow width nMOSFET…71
Fig. 5-14. Vt,lin shifts versus stress time at 25 °C of wide and narrow width devices…72
Fig. 5-15. Vt,lin shifts versus stress time at 75 °C of wide and narrow width devices…73
Fig. 5-16. Vt,lin shifts versus stress time at 125 °C of wide and narrow width
devices…………………………………………………………………73
Fig. 5-17. △Id,sat versus stress time at 25 °C of wide and narrow width devices……74
Fig. 5-18. △Id,sat versus stress time at 75 °C of wide and narrow width devices……75
Fig. 5-19. △Id,sat versus stress time at 125 °C of wide and narrow width devices……75
Fig. 5-20. R-G currents vs. VG of wide width device after PBTI stress at VR=0.2……76
Fig. 5-21. R-G currents vs. VG of wide width device after PBTI stress at VR=0.2……77
Fig. 5-22. R-G currents vs. VG of wide width device after PBTI stress at VR=0.2……77
Fig. 5-23. R-G currents vs. gate voltage of wide width device after PBTI stress at
25℃………………………………………………………………………78
Fig. 5-24. R-G currents vs. VG of wide width device after PBTI stress at VR=0.3V…78
Fig. 5-25. R-G currents vs. VG of wide width device after PBTI stress at VR=0.3V…79
Fig. 5-26. R-G currents vs. VG of wide width device after PBTI stress at VR=0.3V…79
Fig. 5-27. R-G currents vs. gate voltage of wide width device after PBTI stress at
25℃………………………………………………………………………80
Fig. 5-28. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.2V………………………………………………………………81
Fig. 5-29. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.2V………………………………………………………………81
Fig. 5-30. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.2V………………………………………………………………82
Fig. 5-31. R-G currents vs. gate voltage of narrow width device after PBTI stress at
25℃………………………………………………………………………82
Fig. 5-32. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.3V………………………………………………………………83
Fig. 5-33. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.3V………………………………………………………………83
Fig. 5-34. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.3V………………………………………………………………84
Fig. 5-35. R-G currents vs. gate voltage of narrow width device after PBTI stress at
25℃………………………………………………………………………84
Fig. 5-36. R-G currents vs. VG of wide width device after PBTI stress at VR=0.2V…85
Fig. 5-37. R-G currents vs. VG of wide width device after PBTI stress at VR=0.2V…86
Fig. 5-38. R-G currents vs. VG of wide width device after PBTI stress at VR=0.2V…86
Fig. 5-39. R-G currents vs. gate voltage of wide width device after PBTI stress at
75℃………………………………………………………………………87
Fig. 5-40. R-G currents vs. VG of wide width device after PBTI stress at
VR=0.3V………………………………………………………………87
Fig. 5-41. R-G currents vs. VG of wide width device after PBTI stress at VR=0.3V…88
Fig. 5-42. R-G currents vs. VG of wide width device after PBTI stress at VR=0.3V…88
Fig. 5-43. R-G currents vs. gate voltage of wide width device after PBTI stress at
75℃………………………………………………………………………89
Fig. 5-44. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.2V………………………………………………………………90
Fig. 5-45. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.2V………………………………………………………………90
Fig. 5-46. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.2V………………………………………………………………91
Fig. 5-47. R-G currents vs. gate voltage of narrow width device after PBTI stress at
75℃……………………………………………………………………91
Fig. 5-48. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.3V………………………………………………………………92
Fig. 5-49. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.3V………………………………………………………………92
Fig. 5-50. R-G currents vs. VG of narrow width device after PBTI stress at
VR=0.3V………………………………………………………………93
Fig. 5-51. R-G currents vs. gate voltage of narrow width device after PBTI stress at
75℃……………………………………………………………………93
Fig. 5-52. R-G currents vs. VG of wide width device after PBTI stress at
VR=0.2V………………………………………………………………94
Fig. 5-53. R-G currents vs. VG of wide width device after PBTI stress at
VR=0.2V………………………………………………………………95
Fig. 5-54. R-G currents vs. gate voltage of wide width device after PBTI stress at
125℃……………………………………………………………………95
Fig. 5-55. R-G currents vs. VG of wide width device after PBTI stress at
VR=0.3V………………………………………………………………96
Fig. 5-56. R-G currents vs. VG of wide width device after PBTI stress at
VR=0.3V………………………………………………………………96
Fig. 5-57. R-G currents vs. gate voltage of wide width device after PBTI stress at
125℃……………………………………………………………………97
Fig. 5-58. R-G currents vs. VG of wide narrow device after PBTI stress at
VR=0.2V………………………………………………………………98
Fig. 5-59. R-G currents vs. VG of wide narrow device after PBTI stress at
VR=0.2V………………………………………………………………98
Fig. 5-60. R-G currents vs. gate voltage of narrow width device after PBTI stress at
125℃……………………………………………………………………99
Fig. 5-61. R-G currents vs. VG of wide narrow device after PBTI stress at
VR=0.3V………………………………………………………………99
Fig. 5-62. R-G currents vs. VG of wide narrow device after PBTI stress at
VR=0.3V………………………………………………………………100
Fig. 5-63. R-G currents vs. gate voltage of narrow width device after PBTI stress at
125℃……………………………………………………………………100
Fig. 5-64 △Igen,s/W vs. stress fields of wide and narrow width device after stress…101
Fig. 5-65 △Igen,s/W vs. stress fields of wide and narrow width device after stress…102
Fig. 5-66 △Igen,s/W vs. stress fields of wide and narrow width device after stress…102
Fig. 5-67 Interface states creation in wide width nMOSFETs after DAHC stress……103
Fig. 5-68 Interface states creation in narrow width nMOSFETs after DAHC stress…103
Fig. 5-69 Interface states creation in wide width nMOSFETs after CHC stress……104
Fig. 5-70 Interface states creation in narrow width nMOSFETs after CHC stress…104
Fig. 5-71 Interface states creation in wide width nMOSFETs after PBTI stress……105
Fig. 5-72 Interface states creation in narrow width nMOSFETs after PBTI
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[12] D. Fotty, MOSFET Modeling with SPICE. Englewood Cliffs, NJ: Prentice-Hall, 1997, Ch. 6, pp. 113–115.
[13] BSIM Group, MOSFET Model. Univ. California, Berkeley. (online available: http://www-device.eecs.berkeley.edu/~bsim3/)
[14] D. Fotty, MOSFET Modeling with SPICE, Englewood Cliffs, NJ: Prentice-Hall, 1997, Ch. 11, p. 399.
[15] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley, 2000, Ch. 2, p. 26.
[16] J. Mandelman and J. Alsmeir, “Anomalous narrow channel effect in trench-isolated buried channel P-Mosfets,” IEEE Electron Device Lett., vol. 15, Dec. 1994, pp. 496–498.
[17] D. A. Neamen, Semiconductor Physics & Devices, 3rd ed. McGraw-Hill; 2003, P. 248.
[18] F.-C. Chiu, W.-C Shih, J. Y. Lee and H.-L. Hwang “An investigation of surface state capture cross-sections for metal-oxide-semiconductor field-effect transistors using HfO2 gate dielectrics,” Microelectronics Reliability, Volume 47, Issues 4-5, April-May 2007, pp. 548-551.
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