臺灣博碩士論文加值系統

本論文分為兩部份，第一部份為應用於無線射頻辨識系統之移頻調變解調系統，解調系統由交流直流轉換器與解調電路組成。利用整流器與穩壓器組成交流直流轉換器，可以得到一個低漣波電壓的工作電源，提供給解調電路使用。解調電路分有類比式與數位式兩種架構，在類比式解調電路中，我們用多工器、相位頻率檢測器、電荷幫浦與電流控制振盪器來構成。至於數位式解調電路，我們使用多工器、移位暫存器、相位頻率檢測器與電荷幫浦組成。類比式解調系統與數位式解調系統都以台積電0.35μm 2P4M CMOS製程實現，類比式解調系統晶片面積為0.34mm2(不含PAD)，數位式解調系統為0.36mm2(不含PAD)。
第二部份是針對電源系統所中需要的低壓降線性穩壓器提出設計與實現。線性穩壓器穩壓方式是根據輸出電壓與參考電壓之間的電壓差，此差值經由誤差放大器放大後，用來控制功率電晶體的閘極電壓，進而調節負載電流的大小，使輸出電壓受到控制。最後，在輸出端掛上分壓電阻，將輸出電壓分壓後再與電壓調整器的負端相連，使整個系統形成穩定的負回授系統，因此我們可以預先規定輸出電壓大小，在藉由控制機制調整輸出電壓。本電路使用的是台積電0.35μm 2P4M CMOS製程實現，晶片面積為0.25mm2(不含PAD)。

The major research of this thesis can be divided into two parts. The first part of the thesis is to implement a FSK demodulation system for RFID. We proposed an analog demodulation system and a digital demodulation system. The both systems use the same AC-DC converter which provides DC power for demodulation circuit. The analog demodulation circuit is composed of a multiplexer, a phase frequency detector, a charge pump, and a current controlled oscillator. The digital demodulation circuit is composed of a multiplexer, a phase frequency detector, a charge pump, and a shift register. The two demodulation systems are implemented by 3.3V TSMC 0.35μm CMOS 2P4M process. The chip area of analog demodulation system is 0.34mm2 without PAD, and the chip area of digital demodulation system is 0.36mm2 without PAD.
In the second part of this thesis, we presented a current feedback low-dropout voltage regulator. We adopted a simple circuit architecture and replaced voltage feedback by current feedback. Therefore, the characteristics of the proposed LDO are low quiescent current and fast transient response. The LDO is implemented by 3.3V TSMC 0.35μm CMOS 2P4M process. The chip area of LDO is 0.25mm2 without PAD.

目錄
摘要 i
ABSTRACT ii
誌謝 iii
圖目錄 viii
第一章 緒論 - 1 -
1.1 相關研究發展現況 - 1 -
1.2 研究動機 - 3 -
1.3 論文架構 - 4 -
第二章 內建工作電源之FSK解調系統 - 5 -
2.1 FSK調變技術 - 5 -
2.2 解調系統架構 - 6 -
2.2.1 類比式FSK解調系統 - 7 -
2.2.2 數位式FSK解調系統 - 8 -
2.3 交流直流轉換器 - 8 -
2.3.1 整流電路 - 9 -
2.3.2 穩壓電路 - 13 -
2.4 FSK解調電路 - 15 -
2.4.1 解調電路原理說明 - 15 -
2.4.2 多工器 - 16 -
2.4.3 相位頻率檢測器 - 18 -
2.4.4 電荷幫浦 - 22 -
2.4.5 電流控制振盪器 - 24 -
2.4.6 移位暫存器 - 32 -
2.5 FSK解調系統模擬結果 - 36 -
2.5.1 交流直流轉換器模擬結果 - 37 -
2.5.2 類比式解調系統模擬結果 - 38 -
2.5.3 數位式解調系統模擬結果 - 39 -
2.6 FSK解調系統量測結果 - 40 -
2.6.1 類比式解調系統佈局與量測結果 - 40 -
2.6.2 數位式解調系統佈局與量測結果 - 43 -
第三章 低壓降線性穩壓器研究近況與重要參數 - 47 -
3.1 相關研究發展近況 - 47 -
3.2 研究動機 - 48 -
3.3 低壓降線性穩壓器基本原理 - 49 -
3.4 低壓降線性穩壓器重要參數 - 50 -
3.4.1 導通元件的選擇 - 50 -
3.4.2 輸出電容之等效串聯電阻 - 52 -
3.4.3 輸入輸出電壓差 - 54 -
3.4.4 線性調節率 - 55 -
3.4.5 負載調節率 - 56 -
3.4.6 效率 - 57 -
3.4.7 輸出準確率 - 58 -
3.4.8 接地電流 - 60 -
3.4.9 電源拒斥比 - 61 -
3.4.10 輸出雜訊 - 62 -
3.4.11 暫態響應 - 62 -
3.4.12 頻率響應 - 64 -
第四章 電流回授低壓降電壓調整器 - 69 -
4.1 誤差放大器之設計 - 69 -
4.2 第二代電流傳輸器 - 72 -
4.3電流回授低壓降電壓調整器 - 76 -
4.4電流回授低壓降電壓調整器模擬結果 - 79 -
4.4.1 輸入輸出電壓差模擬結果 - 79 -
4.4.2 穩定時間模擬結果 - 79 -
4.4.3 線性調節率模擬結果 - 80 -
4.4.4 負載調節率模擬結果 - 81 -
4.5電流回授低壓降電壓調整器佈局與量測結果 - 82 -
4.5.1 電流回授低壓降電壓調整器晶片佈局 - 82 -
4.5.2 電流回授低壓降電壓調整器量測結果 - 83 -
第五章 結論與未來展望 - 89 -
5.1 結論 - 89 -
5.2 未來展望 - 90 -
參考文獻 - 91 -

[1]J.P. Curty, N. Joehl, C. Dehollain, and M. J. Declercvq, “Remotely Powered Addressable UHF RFID Integrated System,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 11, pp. 2193-2202, Nov. 2005.
[2]U. Karthaus, and M. Fischer, “Fully Integrated Passive UHF RFID Transponder IC with 16.7μW Minimum RF Input,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 10, pp. 1602-1608, Oct. 2003.
[3]Bob Watson, “FSK：Signals and Demodulation,” Tech-note, Watkins Johnson Company, 1980.
[4]Simon Haykin, “Communication system 4th Edition,” Wiley 2001.
[5]X. Wang, B. Jiang, W. Che, N. Yan, and H. Min, “A High Efficiency AC-DC Charge Pump Using Feedback Compensation Technique,” IEEE Asian Solid-State Circuits Conference, Nov. 2007, pp. 252-255.
[6]R. M. Weng, S. Y. Li, and J. C. Wang, “Low Power Frequency-Shift Keying Demodulators for Biomedical Implants,” IEEE Conference on Electron Devices and Solid-State Circuits, Dec. 2007, pp. 1079-1082.
[7]Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000.
[8]劉深淵與楊清淵編著，鎖相迴路，滄海書局，2006。
[9]J. Yuan, and C. Svensson, “Fast CMOS Nonbinary Divider and Counter,” Electronics Letters, Vol. 29, No. 13, pp. 1222-1223, June 1993.
[10]S. Kim, K. Lee, Y. Moon, D. Kyoon, Y. Choi, and H. K. Lim, “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, pp. 691-700, May 1997.
[11]X. Shi, K. Imfeld, S. Tanner, M. Ansorge, and P. A. Farine, “A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication,” Proceedings of the 32nd European Solid-State Circuits Conference, pp. 174-177, Sept. 2006.
[12]I. A. Young, J. K. Greason, J. E. Smith, and K. L. Wong, “A PLL Clock Generator with 5MHz to 110MHz Lock Range for Microprocessors,” IEEE International Solid-State Circuits Conference, Feb. 1992, pp. 50-51.
[13]J. Yuan, and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 1, pp. 62-70, Feb. 1989.
[14]B. Chang, J. Park, and W. Kim, “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 749-752, Feb. 1996.
[15]黃子陽，低壓降線性穩壓器頻率補償之改善方法，國立清華大學，電子工程研究所，碩士論文，民國93年。
[16]李新通，低電源雜訊之電流電壓轉換線性穩壓積體電路研製，國立台北科技大學，電子電腦與通訊產業研發碩士專班，碩士論文，民國96年。
[17]黃照宏，以電流式主動元件為基礎之濾波器與振盪器的設計與實現，國立台北科技大學，電子電腦與通訊產業研發碩士專班，碩士論文，民國96年。
[18]S. I. Liu, H. W. Tsao, J. Wu, T. C. Yu, and T. K. Lin, “Design and Optimization of MOSFET-Capacitor Filters Using CMOS Current Conveyors,” IEEE International Symposium on Circuits and Systems, Vol. 3, May. 1990, pp. 2283–2286.
[19]R. J. Milliken, J. S. Martinez, and E. S. Sinencio, “Full On-Chip CMOS Low-Dropout Voltage Regulator,” IEEE Transaction on Circuit and System I: Regular Papers, Vol. 54, No. 9, pp. 1879-1890, Sept. 2007.
[20]K. N. Leung and P. K. T. Mok, “A Capacitor-Free CMOS Low-Dropout Regulator with Damping-Factor-Control Frequency Compensation,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 10, pp. 1691-1702, Oct. 2003.
[21]S. H. Lu, W. J. Huang, and S. I. Liu, “A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors,” IEEE Asian Solid-State Circuits Conference, Vol.4, May. 2005, pp. 497-500.
[22]S. H. Lu, W. J. Huang, and S. I. Liu, “A Capacitor-Free CMOS Low-Dropout Regulator with Slew Rate Enhancement,” IEEE International Symposium on VLSI Design, Automation, and Test, Apr. 2006, pp. 1-4.
[23]W. J. Huang and S. I. Liu, “Sub-1V Capacitor-Free Low-Dropout Regulator,” Electronics Letters, Vol. 42, No. 24, pp. 1395-1396, Nov. 2006.
[24]S. K. Lau, P. K. T. Mok, and K. N. Leung, “A Low-Dropout Regulator for SoC with Q-Reduction,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 3, pp. 658-664, Mar. 2007.
[25]P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, “Area-Efficient Linear Regulator with Ultra-Fast Load Regulation,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, pp. 933–940, Apr. 2005.
[26]C.K. Chava and J. S. Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators,” IEEE Transaction on Circuit and System I: Regular Papers, Vol. 51, No. 6, pp. 1041–1050, Jun. 2004.
[27]T. Y. Man, P. K. T. Mok, and M. Chan, “A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators with Transient-Response Improvement,” IEEE Transaction on Circuit and System II, Vol. 54, No. 9, pp. 755-759 Sept. 2007.
[28]M. A. Shyoukh, H. Lee, and R. Perez, “A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator with Buffer Impedance Attenuation,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 8, pp. 1732-1742, Aug. 2007.