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研究生:唐有田
研究生(外文):Yu-Tien Tang
論文名稱:可撓曲五環素薄膜電晶體之製備及特性探討
論文名稱(外文):Studies on the Fabrication and Characteristics ofFlexible Pentacene Thin-Film Transistors
指導教授:郭欽湊
指導教授(外文):Chin-Tsou Kuo
學位類別:碩士
校院名稱:大同大學
系所名稱:化學工程學系(所)
學門:工程學門
學類:化學工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:84
中文關鍵詞:可撓曲薄膜電晶體五環素
外文關鍵詞:Thin-Film TransistorsPentaceneFlexible
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本論文研究主要是探討撓曲性薄膜電晶體之特性以五環素為半導
體層,以聚對苯二甲酸乙二酯(poly(ethylene terephthalate); PET)為塑膠基
板分別以聚醯胺樹酯(polyamide resin; PA) 及聚甲基丙烯酸甲酯
(poly(methyl methacrylate); PMMA)作為絕緣層來研究不同絕緣層影響電
晶體之特性, 並分別以1-Octadecanethiol (1-ODT) , 及
Octadecyltrichlorosilane (OTS)作為處理閘極金電極之處理劑來改變閘極
金電極之表面形態,使其進一步改變五環素之結晶特性,進而改善元件
之特性。首先利用Metal-Insulator-Semiconductor元件結構在100 kHz時測定
單層PA,雙層PA/PMMA及PMMA/PA的電容值,分別為1.88、1.94及0.99
nF/cm2。第一部份以單層PA作為絕緣層,其電晶體之位移率0.36
cm2/Vs,開關電流比8.05 × 102,進一步利用1-ODT處理閘極金電極得到
位移率1.04 cm2/Vs,開關電流比1.40 × 103,而利用OTS處理閘極金電極
得到位移率1.33 cm2/Vs、開關電流比2.04 × 105。由XRD之圖形得知當存
在單一結晶相時且強度較強可得到較好之元件特性。且由AFM可得到當
pentacene薄膜表面較平坦且顆粒較大時,可以減少晶隙邊界降低離子陷
阱數目提昇位移率之大小。第二部份利用雙層PA/PMMA作為閘極絕緣層得到位移率0.56
cm2/Vs、開關電流比1.25 × 106;可以發現off current 下降到5 pA,因此
開關電流比可以達到106,比單層PA作為絕緣層的提昇三個次方。以
1-ODT或OTS進一步處理閘極金電極並無明顯之特性增進。第三部份以
雙層PMMA/PA作為閘極絕緣層時元件特性只有位移率0.30 cm2/Vs、開關
電流比5.63 × 103。然可發現元件特性呈現理想的曲線。
The main aim of this thesis studies on the characteristics of flexible
thin-film transistor (TFT) fabricated with pentacene as a semiconductor layer,
poly(ethylene terephthalate) (PET) as a plastic substrate, polyamide (PA) and
poly(methyl methacrylate) (PMMA) acted as polymeric gate dielectric. We
have chosen 1-octadecanethiol (1-ODT) and octadecyltrichlorosilane (OTS)
used as treated agent for gate electrode to change the surface morphology of
gate electrode in order to improve the orientation of the pentacene deposited
on the polymer dielectric and to improvement device characteristics.
The capacitance is 1.88 nF/cm2 of PA, 1.94 nF/cm2 of PA/PMMA and
0.99 nF/cm2 of PA/PMMA dual layer through the measurement on the
architecture of Metal-Insulator-Semiconductor device at a frequency of 100
kHz. Part I, we have chosen PA acted as a polymeric gate dielectric. The
mobility and on/off current ratio of the pentacene TFT are 0.36 cm2/Vs and
8.05 × 102, respectively. Further, the mobility and on/off current ratio of TFT
with gate electrode treated with 1-ODT are 1.04 cm2/Vs and 1.40 × 103,
respectively. The mobility and on/off current ratio of TFT for capping the
surface of gate electrode with OTS are 1.33 cm2/Vs and 2.04 × 105,
respectively. Existence of a single crystal phase with more intensity in theXRD pattern can be obtained the better performance of device. Atom Force
Microscope (AFM) images showed that the surface of pentacene was more
flatness and larger grain size, which can reduce the grain boundaries and the
trap states, to improve the mobility.
Part II, we have chosen PA/PMMA dual layer acted as polymeric gate
dielectric. The mobility and on/off current ratio are 0.56 cm2/Vs and, 1.25 ×
106, respectively. It is found that the leakage current reduced significantly tobe 5 pA such that the on/off current ratio increased to about 106, which is
three orders of magnitude larger than that of device with PA gate dielectric.
However, the improvement on the characteristics of TFT with 1-ODT or
OTS treated gate electrode is unobvious. Part III, we have chosen PMMA/PA
dual layer acted as polymeric gate dielectric. The mobility and on/off current
ratio are only 0.30 cm2/Vs and 5.63× 103, respectively, but the I-V curves of
the device exhibit the ideal characteristics.
目 錄
摘要(中文i
摘要(英文)iii
目錄 v
表目錄 vii
圖目錄 viii
第一章 前言 1
第二章 文獻回顧 6
2.1 有機薄膜電晶體概論 6
2.2 各項重要參數 10
2.2.1 載子遷移率(Mobility)10
2.2.2 起始電壓(Threshold voltage; VT) 11
2.2.3 次臨界斜率(Subthreshold slope,SS)12
2.2.4 電流開關比(On/off current ratio)13
2.3有機半導體薄膜製備 14
2.4 文獻回顧 16
2.5 研究動機 20
第三章 實驗部分 21
3.1 藥品 21
3.2 可撓式有機薄膜電晶體製備 22
3.3 Metal-Insulator-Semiconductor (MIS)結構製作23
3.4 儀器 24
第四章 結果與討論 25
4.1 前言 26
4.2 以Metal-Insulator-Semiconductor(MIS)量測絕緣層之電容 27
4.3 改變不同絕緣層加熱處理溫度對五環素沈積之影響 29
4.4 不同基板溫度對於元件特性之影響 32
4.5 單層PA 絕緣層以1-ODT 處理閘極金電極對元件特性之影響34
4.6 單層PA 絕緣層以OTS 處理閘極金電極對元件特性之影響 46
4.7 以PA 及PMMA 作為雙層絕緣層 55
4.8 以1-ODT 及OTS 處理閘極金電極並以PA/PMMA 作為雙層絕緣層68
參考文獻 76
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