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研究生:陳彥志
研究生(外文):Yen-Chih Chen
論文名稱:以FPGA為基礎的多處理器系統單晶片之設計及實作
論文名稱(外文):Design and Implementation of Multiprocessor Systemon a Chip (MPSoC) Based on FPGA
指導教授:曾嘉影
指導教授(外文):Chia-Ying Tseng
學位類別:碩士
校院名稱:大同大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:28
中文關鍵詞:場域可程式化閘陣列Nios II多處理器多核心軟核心
外文關鍵詞:FPGANios IIMultiprocessorSoft-coreMulti-core
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隨著當今各種多媒體影音壓縮標準的日新月異,要能負擔如此龐大的運算已經不再是單一核心的處理器能夠做到,大家轉而去嘗試是否能運用多個處理器來處理需要大量運算的程式,而嵌入式系統的平台也從單核心轉變到雙核心甚至是多核心的處理器系統。
在本篇論文中,我們使用Nios II 軟核心建構MPSoC 的架構,設計並實作一個四核心的處理器系統(包含4K I-cache、1MB SRAM、32 MB SDRAM、16MB Flash),然後利用硬體互斥元件設計多處理器上所執行的軟體,使其能夠達成互斥存取共享的記憶體元件。以此實作結果顯示,我們所提出之以軟核心為主的可組態多處理器系統是能夠四核心同時交互運行。
隨後我們針對四個處理器的平台相較於一個、兩個及三個處理器的平台去執行兩個不同的測試程式來做效能的評估與分析。其中一種是透過單一變數去宣告,共享資源存取有一個客制化的順序;另一種是透過陣列去宣告,共享資源的存取不需要順序。結果顯示,不需要順序控制的程式其加速比的上升速度較快。
With the growing of multimedia codec types, the huge amount of produced computing can not be handled by a single processor now. Therefore, we hope that the programs which include many computations can be processed by multiprocessors. In addition, the core operated in embedded system platform also gradually becomes multiprocessor from a single processor.
In the thesis, we design a four-processor system using NiosII soft-core and implement our MPSoC architecture (includes 4K I-cache, 1MB SRAM, 32MB SDRAM, 16MB
Flash) and design the executable programs running in multiprocessor via hardwire Mutex element. We use the hardwire Mutex core to access the shared memory in the program. The implemented result shows that the quad-core system architecture that we proposed can execute the program concurrently at the same time.
After the system is working, we evaluate and analyze the system performance by writing two programs in our four-core platform compared with one, two and three processors system. One of those declares a single variable and it accesses share data via a custom access order. The other case computes with array data type and accesses share data out of order. The result shows that the speedup without accessing order gets the higher increasing rate.
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 BACKGROUND 3
2.1 Autonomous multiprocessor system 3
2.2 Non-Autonomous Multiprocessor System 4
2.3 The shared system resources 5
2.3.1 Shared Memory 5
2.3.2 Shared Bus 6
2.3.3 Shared Peripherals 6
CHAPTER 3 Design of Multiprocessor System on a Chip (MPSoC) 7
3.1 System Architecture 7
3.2 Hardware/Software Specification 8
3.2.1 Hardware Specification 8
3.2.2 Software Specification 8
3.3 The system component being used 9
3.3.1 Soft-Core Processor NiosII 9
3.3.2 Mutex Core 10
3.3.3 Avalon Bus 12
CHAPTER 4 IMPLEMENTATION 14
4.1 System Design Flow 14
4.2 Description of Relative Program 15
4.3 System Implementation 17
4.4 Performance Evaluation 20
4.4.1 Variable Computation in Order 20
4.4.2 Array Computation Out of Order 21
4.4.3 Performance Evaluation and Analysis 22
CHAPTER 5 CONCLUSION AND FUTURE WORKS 26
REFERENCES 27
[1] L. Benini and G. de Micheli, “Networks on chips: A new SoC paradigm,” Proceedings of the IEEE Computer, vol. 35, No. 8, Jan. 2002, Pages 70-78.
[2] Sheldon, D. Kumar, R. Vahid, F. Tullsen, D. Lysecky, “Conjoining Soft-Core FPGA Processors,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Nov. 2006, Pages 694-701.
[3] K. Compton, “Reconfigurable Computing: A Survey of Systems and Software,” Proceedings of the ACM Computing Surveys, vol. 34, No. 2, Jun 2002, Pages171-210.
[4] A. Jerraya and W. Wolf, “Guest Editors' Introduction: Multiprocessor Systems-on-Chips,” Proceedings of the IEEE Computer, vol. 38, No. 7, Jul. 2005, Pages 36-40.
[5] Chia-Ying Tseng, Liang-Teh Lee, Chun-Hung Chen, and Yen-Chih Chen, “A Soft-Core Based Reconfigurable Multiprocessor System,” Proceedings of 2007 National Computer Symposium, Vol. 2, pp. 437-443
[6] Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko H�躪nik�韉nen, and Timo D. H�讜�纜�韉nen , “A parallel MPEG-4 encoder for FPGA based multiprocessor SoC,” Field Programmable Logic and Applications, 2005. International Conference on .
[7] Altera, “Cyclone II FPGA Starter Board Reference Manual,” Altera Corporation, October 2007.
[8] Altera, “Nios II Processor Reference Handbook,” Altera Corporation, October
2007.
[9] Altera, “Profiling Nios II Systems,” Altera Corporation, February 2006.
[10] Altera, “Nios II Hardware Development Tutorial,” Altera Corporation, October 2007. 28
[11] Altera, “Creating Multiprocessor Nios II Systems Tutorial,” Altera Corporation, December 2007.
[12] Altera, “Quartus II Handbook Volume 4: SOPC Builder,” Altera Corporation, October 2007.
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