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研究生:邱顯駿
研究生(外文):Shian-Jiun Chiou
論文名稱:轉換SysML規格到SystemCTLM
論文名稱(外文):Translating SysML Specification to SystemC Transaction-Level Modeling
指導教授:鄭福烱
指導教授(外文):Fu-Chiung Cheng
學位類別:碩士
校院名稱:大同大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:41
中文關鍵詞:系統模擬語言
外文關鍵詞:SysMLSystemCTLM
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隨著各種3C產品不斷的發展,新產品的生命期越來越短,Time to Market變的非常重要。因為新的技術需要通常需要更多電晶體數量,以及新產品有更多的新功能,使得產品設計的複雜度越來越高。因為time to market以及產品複雜度的問題,我們急需一種新式系統層級的晶片設計方法,來加快晶片的設計速度。
本論文提出了一個合成的方法,能從用SysML來描述我們系統需求後轉換到可執行的SystemC TLM code上。我們用洗衣機系統當做例子來敘述我們轉換的方法,並且延伸了use case和sequence diagram使得它們能夠描述操作的順序性以及平行的行為。我們會詳細說明如何使用block definition diagrams, internal block diagrams和extended sequence diagrams來轉換到SystemC TLM code。
As 3C’s products become more and more popular and product lifetime becomes much shorter, how to shorten time to market becomes very important issue. Design complexity of these products increases dramatically due to huge amount of transistors available in new process technology and new functionality required in new products. To deal with time to market issue and design complexity problem, a new system level design methodology is indispensable.
This thesis proposes a synthesis methodology to translate system requirement modeled in SysML into an executable transaction level model (TLM) in SystemC[5]. A case study on washing machine design is used to illustrate our methodology. We extend use case and sequence diagrams new capabilities to model operation order and parallel behaviors, respectively. How to map block definition diagrams and internal block diagrams and extended sequence diagrams in SysML to modules, ports and processes in SystemC are described in detail.
ABSTRACT i
中文摘要 ii
Table of Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Structure 2
Chapter 2 Background 3
2.1 SysML 3
2.1.1 Block Definition Diagram 4
2.1.2 Internal Block Diagram 5
2.2 SystemC 6
2.2.1 SystemC Transaction-level modeling 7
2.2.2 TLM Types 8
Chapter 3 Implementation-Diagrams 9
3.1 Context diagram 10
3.2 Extended Use case diagrams 10
3.3 Use case analysis 11
3.4 Collect blocks of BDD 14
3.5 Parallel sequence diagram 15
3.6 Discriminate Hw/Sw parts 17
3.7 IBD 18
Chapter 4 Implementation -Translate 20
4.1 Generate SystemC classes 22
4.2 Generate SystemC ports 23
4.3 Generate SystemC processes 24
4.4 Generate Top level module 26
4.5 Port mapping 27
Chapter 5 Results 29
Chapter 6 Conclusions and Feature Works 31
References 33
[1]Cai L., Gajski D., ”Transaction level modeling: an overview”, First IEEE/ACM/IFIP International Conference on Hardware / Software Codesign and System Synthesis, Oct. 2003.
[2]Habibi A., Tahar S., “Design for verification of SystemC transaction level models”, Design, Automation and Test in Europe, 2005.
[3]Huang E., Ramamurthy R., McGinnis L.F., “System and simulation modeling using SYSML”, Simulation Conference, 2007
[4]Mauro Prevostini, Elena Zamsa, ”SysML Profile for SoC Design and SystemC Transformation”, ALaRI, Faculty of Informatics University of Lugano via G. Buffi 13, CH-6904 Lugano, May 11,2007.
[5]Raslan W., Sameh A., “System-Level Modeling and Design Using SysML and SystemC”, Integrated Circuits, 2007. ISIC '07. , Sept. 2007
[6]Schirner G., Domer R., ”Result-Oriented Modeling—A Novel Technique for Fast and Accurate TLM”, Computer-Aided Design of Integrated Circuits and Systems, pp.1688 – 1699, Sept. 2007.
[7]SysML, http://www.sysmlforum.com/
[8]UML, http://www.uml.org/
[9]Vrancken J., ”Requirements specification and modeling through SysML”, IEEE International Conference, pp. 1735-1740, Oct. 2007
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