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研究生:林佳輝
研究生(外文):Chia-Hui Lin
論文名稱:轉換SystemCTLM模型到RTL模型
論文名稱(外文):Toward Translating SystemC Transaction Level Model to RTL Model
指導教授:鄭福炯鄭福炯引用關係
指導教授(外文):Fu-Chiung Cheng
學位類別:碩士
校院名稱:大同大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:46
中文關鍵詞:轉換匯流排
外文關鍵詞:translateSystemCTLMbus
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電路製程技術的進步使得晶片上的功能愈來愈強大。但這也使得系統設計越來越複
雜。然而電子產品的生命週期卻愈來愈短,更加深了產品上市時程(Time to Market)
的壓力。如何減少系統複雜度以符合上市時程就成為重要的議題。
使用較高層級的TLM 來描述系統比用RTL 更有效率而且快速。在SystemC
TLM 中有許多重要的模組例如處理器和匯流排,其中好的匯流排架構能使得系統運
作得更有效率。本論文研究如何在三種不同的TLM 模型中實作一般匯流排(general
bus),並且提出了一個方法將SystemC TLM 的一般匯流排轉換成為RTL 的匯流排
模型(WISHBONE 和Avalon)。藉此縮短開發時程以符合上市時程的需求。
The improved circuit design technology makes the functionality on a chip more and more powerful, but this also causes high system design complexity. The life cycle of electronic circuit of products is getting shorter and shorter. This causes more pressure of time to market. How to shorten time to market becomes an important issue.
Describing the system with high-level TLM (Transaction-level model) is more
efficient and faster than describing with RTL (Register transfer level). There are many important modules in TLM such as processor and bus. Well designed bus architecture can make system work efficiently. In this thesis we investigate how to implement general bus in three different TLMs and propose a methodology to translate the TLM general bus to RTL bus model (WISHBONE and Avalon). Our methodology can reduce design complexity and satisfy the requirement in time to market.
摘要 i
ABSTRACT ii
LIST OF FIGURES iv
LIST OF TABLES vi
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Research Methods 2
1.3 Thesis Structure 2
CHAPTER 2 BACKGROUND 3
2.1 SystemC 3
2.2 Mainly On-Chip Bus 4
2.2.1 AMBA(Advanced Microcontroller Bus Architecture) 4
2.2.2 Avalon 5
2.2.3 WISHBONE 5
CHAPTER 3 TLM GENERAL BUS 8
3.1 General Bus in Component-assembly Model 8
3.2 General Bus in Bus-arbitration Model8
3.3 General Bus in Bus-functional Model 9
3.4 Comparison of three TLMs 11
CHAPTER 4 TRANSLATION TLM TO RTL BUS 12
4.1 The Structure of Bus Profile 13
4.2 Translating TLM to RTL Model Algorithm 14
4.2.1 Port Insertion and Deletion 14
4.2.2 Process Insertion and Deletion 15
3.3.3 Set Number of Master and Slave 16
4.2.4 Choose Arbitration 17
4.2.5 Port Mapping 17
CHAPTER 5 EXAMPLES AND RESULTS 18
5.1 Toward Translating General Bus to WISHBONE 18
5.2 Toward Translating General Bus to Avalon 25
5.3 Results 33
CHATPER 6 CONCLUSIONS AND FUTURE WORKS 35
6.1 Conclusions 35
6.2 Future Works 35
REFERENCES 36
[1] Open SystemC Initiative, 2006. http://www.systemc.org/
[2] 楊佳玲/黃靖傑, “SoC設計探索:善用新一代硬體描述語言SystemC軟硬體共同
模擬加速產品上市,” 新電子233 期八月號, 2005.
http://www.mem.com.tw/technologyexploring_content.asp?sn=0701020435
[3] Stuart Swan, Cadence, “A Tutorial Introduction to the SystemC TLM Standard,”
2006.
http://www-ti.informatik.uni-tuebingen.de/~systemc/Documents/Presentation-13-
OSCI_2_swan.pdf
[4] 繆永良, “SystemC語言概論,” 國家晶片系統設計中心, 2005.
http://140.113.34.204/Uploads/15_SystemC%E8%AA%9E%E8%A8%80%E6
%A6%82%E8%AB%96_%E4%B8%8B155530.pdf
[5] CTO Drew Wingard, Sonics Inc.; Pascal Chauvet , CoWare,
http://www.eettaiwan.com/ART_8800380422_480102_NT_1d2aa797.HTM
[6] AMBA specification, Rev 2.0, ARM Inc., 1999.
http://www.arm.com/products/solutions/AMBA_Spec.html
[7] Avalon Bus Specification, Altera Corporation,
http://www.altera.com/products/ip/altera/t-alt-atlantic.html
[8] WISHBONE specification, Rev B.3, Silicore Inc., 2003.
http://www.pldworld.com/_hdl/2/_ip/-silicore.net/pdfiles/wishbone/specs/wbspe
c_b3.pdf
[9] Lukai Cai,Daniel Gajski, “Transaction Level Modeling: An Overview,” First
IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and
System Synthesis, Page(s):19 – 24, 2003
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