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研究生:陳信宇
研究生(外文):Hsin-Yu Chen
論文名稱:採用無負載及切換式運算放大器共享技術之一伏特十位元10MSample/s管線式類比數位轉換器
論文名稱(外文):A 1-V, 10BIT, 10MSAMPLE/S SWITCHED-OPAMP PIPELINED ADC USING LOADING-FREE AND OPAMP-SHARING TECHNIQUES
指導教授:黃淑絹黃淑絹引用關係
指導教授(外文):Shu-Chuan Huang
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:58
中文關鍵詞:管線式類比數位轉換器切換式運算放大器運算放大器共享無負載技術
外文關鍵詞:pipelined ADCswitched-opampopamp-sharingloading-free
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本篇論文主要描述一個低功率、10位元、操作頻率在10MHz而工作電壓在1V的管流式類比數位轉換器之設計,並提出利用切換式運算放大器共享技術搭配無負載技術來減少轉換器元件數量。有別於一般的低功率低電壓電路,本架構不需要過多的運算放大器以及電容,單純利用開關切換達到無負載以及運算放大器共用。本轉換器採用標準0.18um 1P6M CMOS製程,並透過Hspice模擬電路架構,本轉換器操作在10MHz的取樣頻率,工作電壓為1V,輸入頻率為595kHz下最大SNDR為55.13dB,其總功率消耗為19mW,佈局面積約為1.38mm×1.38mm,完整的測試報告將由日後提出。
In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisted of 1.5-bit/stage has been designed and implemented in TSMC 0.18-µm 1P6M CMOS process. In order to operate at 1 V, the pipelined analog-to-digital converter uses switched-opamp technique. In addition, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the power consumption. An opamp with two output stages is employed to merge opamp-sharing and switched-opamp structures. The passive sample-and-hold (S/H) replaces the conventional sample-and-hold circuit to save power. This work only needs five opamps in the pipelined ADC. Therefore, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption. The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 55.13 dB with sampling frequency of 10 MHz at input frequency of 595 kHz. Power consumption of this ADC is 19mW with 1V power supply. The chip area of this pipelined ADC is 1.38mm×1.38mm without digital error correction. The measurement results will be reported later.
ACKNOWLEDGEMENTS i
ENGLISH ABSTRACT ii
CHINESE ABSTRACT iii
TABLE OF CONTENTS iv
LIST OF FIGURES vii

CHAPTER
I. INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 3
II. REVIEW OF PIPELINED ADCS AND LOW-VOLTAGE SC CIRCUITS 5
2.1 Introduction of Pipelined ADC 5
2.1.1 Conventional Pipelined ADC 6
2.1.2 1.5 Bit/Stage for Pipelined ADC 7
2.2 Switched-Capacitor Circuit in Low-Voltage 9
2.2.1 Conventional SC Circuit 9
2.2.2 Problem at Low-Voltage SC Circuit 10
2.2.3 Switched-Opamp 12
2.3 Opamp-Sharing Technique 13
2.4 Loading-Free Technique 14
III. DESIGN OF PIPELINED ADC 16
3.1 Specification of Pipelined ADC 16
3.1.1 Choice of Capacitors’ Size in Pipelined ADC 17
3.1.2 Specification of Opamp 20
3.2 Input Stage in Low-Voltage Pipelined ADC 21
3.3 Design of MDAC with Opamp-sharing and Loading-free Techniques 23
3.4 Simulation of The MDAC of One-Stage Pipelined ADC 30
IV. CIRCUIT DESIGN AND SIMULATION RESULTS 32
4.1 Design and Simulation of The Opamp 32
4.1.1 Opamp Design 32
4.1.2 SC-CMFB: 35
4.1.3 Simulation of The Opamp: 36
4.2 Design of The Clock Generator 39
4.3 Sub-ADC 41
4.3.1 Design of Dynamic Comparator 41
4.3.2 Simulation of The Comparator and Sub-ADC 43
4.4 Simulation of the Proposed Low-Voltage Pipelined ADC 46
V. CONCLUSIONS 54
5.1 Conclusions 54
5.2 Future Work 54
REFERENCES 56
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