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研究生:傅家德
研究生(外文):Chia-Te Fu
論文名稱:使用切換電容可調式共振器之雙取樣三位元四階帶通差和調變器設計
論文名稱(外文):A double-sampling three-bit fourth-order band-pass delta-sigma modulator based on SC tunable resonators
指導教授:黃淑絹黃淑絹引用關係
指導教授(外文):Shu-Chuan Huang
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:88
中文關鍵詞:可調式帶通差和調變器雙取樣
外文關鍵詞:band-pass delta-sigma modulatorDouble-samplingtunable
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  • 被引用被引用:0
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  • 下載下載:40
  • 收藏至我的研究室書目清單書目收藏:0
在本篇論文中,我們提出以前饋式架構為基礎的可調式共振器之雙取樣三位元四階帶通差和調變器,並以1.5伏電壓的放大器來實現電路中的共振器。在前饋式架構中的共振器僅需處理量化雜訊,避免原始訊號經由電路上共振器的非線性所造成失真的影響。使用可調式共振器,可以針對寬頻或窄頻運用規格所需要的超取樣比值 (OSR) 調整架構上的參數,以選取雜訊轉換函數之最佳陷波 (notch) 頻率。此外,利用雙取樣技術,不但提高取樣頻率且可舒緩放大器速度上的規格要求。
整體實現是用MATLAB和SIMULINK模擬理想和非理想的系統層級架構,藉此得到最佳的參數值。接著利用Hspice作電晶體層級的模擬,使用1.5伏電壓及TSMC 0.18um CMOS 1P6M製程參數。此調變器的時脈頻率為40MHz (相當於80MHz的取樣頻率),輸入中心頻率為20MHz。在頻寬為5MHz (OSR=8),其訊雜比在輸入為-6dBFS是50.26dB;在頻寬為0.625MHz (OSR=64),其訊雜比在輸入同樣為-6dBFS是66.97dB,整體功率消耗為37mW。
In this thesis, we propose a double-sampling three-bit fourth-order band-pass delta-sigma modulator based on switched-capacitor (SC) tunable resonators. With the feedforward topology, the resonators only need to process quantization noise, which can prevent linearity of the input signal affected by resonators. The tunable resonator can be adjusted to obtain the optimum notch frequencies of the noise transfer function according to the bandwidth. Additionally, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier.
The design is carried out as follows. First, MATLAB and SIMULINK are used to simulate the ideal and non-ideal system-level topology, and the design parameters can be optimized. Then, the transistor level simulation is done by Hspice with TSMC 0.18um CMOS 1P6M models. The clock frequency of the modulator is 40MHz (effective frequency would be 80MHz), and the input center frequency is 20MHz. For a 1.5V supply, the SNR is 50.26dB and 66.97dB with -6dBFS input for bandwidth 5MHz (OSR=8) and bandwidth 0.625MHz (OSR=64), respectively. The power consumption is 37mW.
ENGLISH ABSTRACT i
CHINESE ABSTRACT ii
ACKNOWLEDGEMENT ii
CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES xi
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS OUTLINE 2
CHAPTER 2 DELTA-SIGMA CONVERTER 3
2.1 BASIC THEORY 3
2.1.1 A/D Converter 3
2.1.2 Quantization 5
2.1.3 Sampling 8
2.1.4 Oversampling 9
2.2 DELTA-SIGMA MODULATOR 11
2.2.1 First-Order Low-Pass ΔΣ Modulator 13
2.2.2 Low-Pass to Band-Pass Transformation 14
2.2.3 Application of Band-Pass ΔΣ Modulator 16
CHAPTER 3 THE DESIGN OF BAND-PASS DELTA-SIGMA MODULATOR 17
3.1 TOPOLOGY OF BAND-PASS ΔΣ MODULATOR 17
3.1.1 Conventional Band-Pass ΔΣ Modulator 17
3.1.2 Low-Distortion Structure of Band-Pass ΔΣ Modulator 19
3.2 IMPLEMENT OF THE RESONATOR 20
3.2.1 Resonator Types 20
3.2.2 Conventional Tunable Resonator 22
3.2.3 Novel Tunable Resonator 24
3.2.4 Problem of the Double Sampling Technique 30
3.3 MULTI-BIT QUANTIZATION 31
3.4 SYSTEM-LEVEL SIMULATION WITH MATLAB AND SIMULINK 32
3.4.1 Optimized Loop Gain Parameter 32
3.4.2 Optimized Tunable Parameter 34
3.4.3 Non-Ideal Conditions 36
3.4.3.1 Clock Jitter Modeling 37
3.4.3.2 Thermal and Operational Amplifier Noise Modeling 38
3.4.3.2.1 Switches Thermal Noise 38
3.4.3.2.2 Operational Amplifier Noise 39
3.4.3.3 Capacitor Mismatch 40
3.4.3.4 Operational Amplifier Non-Idealities Modeling 42
3.4.3.4.1 Finite DC Gain 43
3.4.3.4.2 Band-Width (BW) and Slew-Rate (SR) 44
3.4.3.4.3 Saturation 47
3.4.4 Simulation Result 47
CHAPTER 4 CIRCUIT IMPLEMENT AND SIMULATION 50
4.1 DESIGN OF THE OPERATIONAL AMPLIFIER 50
4.2 BIAS CIRCUIT 56
4.3 MULTI-BIT QUANTIZER AND DAC 57
4.4 CLOCK GENERATOR 60
4.5 SWITCH 63
4.6 HSPICE SIMULATION RESULTS 64
4.7 PROTOTYPE AND MEASUREMENT 67
CHAPTER 5 CONCLUSIONS 72
5.1 CONCLUSIONS 72
5.2 FUTURE WORK 72
REFERENCES 73
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