(3.238.235.155) 您好!臺灣時間:2021/05/11 19:34
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:王健祐
研究生(外文):Chien-Yu Wang
論文名稱:可適應性頻寬且穩定控制的快速鎖相迴路
論文名稱(外文):AN ADAPTIVE BANDWIDTH AND STABLE CONTROL FOR FAST LOCKED PLL
指導教授:蔡明傑蔡明傑引用關係
指導教授(外文):Ming-Chieh Tsai
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:79
中文關鍵詞:鎖相迴路低抖動快速鎖定適應性
外文關鍵詞:low jitterfast-lockedadaptivePLL
相關次數:
  • 被引用被引用:0
  • 點閱點閱:263
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:115
  • 收藏至我的研究室書目清單書目收藏:0
在設計鎖相迴路有幾個重要的問題要考慮的是:1.低抖動(Low-jitter) 2.低功率消耗(Low-power) 3.較寬的線性區範圍(Linearity region) 4.快速鎖定(Fast-locked),本論文的設計則著重在快速鎖定上。
因此提出一個可適應性控制偵測電路之類比鎖相迴路架構,以一個新的適應性控制迴路的頻寬並且穩定的有效降低鎖定時間與低抖動特性,而且此可適性特色是藉由鎖定的狀況去做電流上的控制進而影響改變頻寬。
本篇論文所使用的製程為 TSMC 0.18 1P6M CMOS的技術,其鎖定時間約為800ns,鎖定時間比傳統鎖相迴路降低了50%以上,在功率消耗上約為23mW, 鎖相迴路的抖動大小約為24ps在2GHz的輸出頻率上.

關鍵詞:適應性, 快速鎖定, 低抖動, 鎖相迴路.
To design a PLL must consider several conditions as the following:1. Low-jitter. 2. Low-power. 3. Wider linearity region. 4. Fast-locked. The thesis focuses on Fast-locked.
Therefore, this thesis presents the analog adaptive PLL architecture with a new adaptive controlled detector to reduce locking time and low jitter in PLL stably. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status.
The proposed architecture is realized in a standard TSMC 0.18 1P6M CMOS technology. The locking time is approximately 800ns and is reduced over 50% than the conventional PLL, power consumption is about 23mW and jitter magnitude is about 24ps on 2GHz.

Keywords:adaptive, fast-locked, low jitter, PLL.
中文摘要 i
ABSTRACT ii
ACKNOWLEDGEMENTS iii
TABLE OF CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES x
CHAPTER 1 Introduction 1
1.1 Motivation 1
1.2 The types and brief introductions of PLL 2
1.2.1 Linear Phase Locked Loop 2
1.2.2 Half-Digital Phase Locked Loop 3
1.2.3 All-Digital Phase Locked Loop 4
1.3 Function of the Adaptive Bandwidth 5
CHAPTER 2 The Concept of Phase-Locked Loop 7
2.1 PLL Background Theory 7
2.1.1 PLL linear model 8
2.2 Phase Frequency Detector (PFD) 10
2.2.1 Charge Pump (CP) 11
2.2.2 Loop Filter (LF) 13
2.2.3 Voltage-Controlled Oscillator (VCO) 15
2.2.4 Frequency Divider (FD) 17
2.3 The closed loop of PLL system design 18
2.3.1 Second order for PLL analysis 18
2.3.2 Third order for PLL analysis 20
CHAPTER 3 Adaptive Bandwidth PLL Design Flow 24
3.1 The principle of adaptive bandwidth PLL design 24
3.2 Several high performance PLL examples 25
3.2.1 A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase Locked Loop 26
3.2.2 A Low Jitter Phase-lock Loop Based on a New Adaptive Bandwidth Controller 28
3.2.3 A Stabilization Technique for Phase-Locked Frequency Synthesizers 30
3.2.4 Design of Low Jitter Adaptive-Bandwidth Charge Pump PLL with Passive Filter 31
3.3 System format and analysis of theory in designing PLL 34
CHAPTER 4 Adaptive Bandwidth PLL Circuit Realization 35
4.1 Architecture of the Proposed PLL 35
4.2 The analysis of non-linearity properties for PFD 36
4.2.1 Dead Zone 36
4.2.2 Operation Frequency 37
4.2.3 Phase Offset 37
4.3 The design of non-linearity PFD 38
4.4 The circuit of improved dead zone for PFD 40
4.5 The circuit of Charge Pump 41
4.5.1 Charge Pump with a new adaptive bandwidth controller 43
4.6 The circuit design and analysis of Low Pass Filter 46
4.7 The circuit design of Voltage Controlled Oscillator (VCO) 47
4.7.1 The types of VCO 47
4.7.2 The circuit design of improved VCO 49
4.8 The circuit design of a new adaptive controlled detector 55
4.9 The frequency divider 56
4.10 Simulation and Result 58
CHAPTER 5 CONCLUSION 62
REFERENCES 63
[1]B. Razavi, Design of Analog CMOS Integrated Circuits, International Edition 2001, McGraw 2001.
[2]H. Kondoh et al., “A 1.5V 250MHz to 3.0V 622MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector,” IEICE Trans. Electron, vol. E78-C, no. 4, pp.381-388, April, 1995.
[3]H. Johansson et al., “A Simple Precharged CMOS Phase Frequency Detecor”, IEEE Journal of Solid-State Circuits. Vol.33, no. 2, pp, 295-299, Feb. 1998.
[4]S. Kim et al., “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE Journal of Solid-State Circuits. Vol.32, no. 5, pp, 691-699, MAY. 1997.
[5]F. M. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. Common, vol.COM-28, pp.1849-1858, Nov. 1980.
[6]R. E. Best, Phase-Locked Loops, Second Ed., New York: McGraw-Hill, 1993.
[7]F. M. Gardner, Phase lock Techniques, Second Ed., New York: Wiley & Sons, 1979.
[8]B. Razavi, Monolithic phase-locked loops and clock recovery circuits, theory and design, IEEE press, 1996.
[9]B. Razavi, Design of Analog CMOS Integrated Circuit, New York: McGraw-Hill, 2001.
[10]Y. Tang, M. Ismail, and S. Bibyk, “Adaptive Miller capacitor multiplier for compact on-chip PLL filter,” Electronics Letters, vol.39, Issue: 1, pp.43-45, Jan. 2003.
[11]H. H. Chang and J.-C. Wu, “A 723-MHz 17.2mw CMOS programmable counter,” IEEE Journal of Solid-State Circuits, vol.33, pp.1572-1575, Oct. 1998.
[12]K. H. Cheng, W. B. Yang, and C. M. Ying, “A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop,” IEEE J. Transactions on Circuits and System, vol.50, pp.892-896, Nov. 2003.
[13]C. Hur, Y. S. Choi, H. H Choi, T. H. Kwon, “A Low Jitter Phase-Lock Loop Based on a New Adaptive Bandwidth Controller,” in proc. IEEE Asia-Pacific Conference on Circuits and Systems, vol.1 pp.421-424, Dec 6-9, 2004.
[14]T. C. Lee and B. Razavi, “A Stabilization for Phase-Locked Frequency Synthesizers,” IEEE Journal of Solid-State Circuits, vol.38, pp.888-894, June 2003.
[15]S. Ying, W. Yuan, J. Song, Z. Baoying, and J. Lijiu, “Design of Low Jitter Adaptive-Bandwidth Charge Pump PLL with Passive Filter,” in proc. ASIC, 2007. 7th International Conference on 22-25, Oct. 2007.
[16]K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura, and M. Yamashina, “A 0.10um CMOS, 1.2V, 2GHz Phase-Locked Loop with Gain Compensation VCO,” in proc. IEEE Custom Integrated Circuits Conference. 2001.
[17]H. O. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE Journal of Solid-State Circuits, vol. 33, no.2, pp. 295-299, Feb. 1998.
[18]K. H. Chen and Y. L. Lo, “A fast-lock DLL with power-on reset circuit,” ISCAS 2004, vol. 4, pp. 357-360, May 2004.
[19]B. Razavi, RF Microelectronics, Prentice-Hall PTR, 1998.
[20]J. Lee, B. Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145 August 2000.
[21]J. Li, F. Yuan, “A new bang-bang phase/frequency detector for fast locking of phase-locked loops,” Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on 5-8 Aug. 2007.
[22]J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊
 
系統版面圖檔 系統版面圖檔