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研究生:余尚珉
研究生(外文):Sheng-Min Yu
論文名稱:採用無負載及運算放大器重設切換技術之一伏特十位元5-MS/s管線式類比數位轉換器
論文名稱(外文):A 1-V 10-BIT 5-MS/S PIPELINED ADC USINGLOADING-FREE AND OPAMP-RESET SWITCHINGTECHNIQUES
指導教授:黃淑絹黃淑絹引用關係
指導教授(外文):Shu-Chuan Huang
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:63
中文關鍵詞:類比數位轉換器低電壓
外文關鍵詞:analog-to-digital converterlow voltage
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電晶體臨界電壓雖然會隨製程精進而下降,但因漏電流等因素其
下降率不大,所以以往在管流式類比數位轉換器的電路在低電壓的情
況下不能獲得足夠的動態範圍。因此,有些方法被提出以克服這個問
題。在本篇論文中,我們使用差動式運算放大器重設切換技巧設計出
一個10 位元5Msample/s 低電壓的管流式類比數位轉換器。同時應用
一種新的低負載架構去降低電容性負載進而改善工作速度。一些常見
應用在低電壓的方法,也同時在本篇論文中加以描述。
Because the threshold voltage of transistors does not scale with the
technology, circuits used in the pipelined ADC in the past could not
obtain the desired dynamic range in low voltage. Several solutions have
been proposed to overcome the problem. In this thesis, a 1-V 10-bits
5Msamples/s pipelined ADC is designed using the fully differential
opamp-reset-switching technique (ORST) to circumvent the speed
problem of switched-opamp technique. A novel loading-free architecture
is also employed to reduce the capacitive loading and to improve the
speed in low-voltage technique. In addition, several approaches to
overcome the low voltage issue are also described.
ABSTRACT I
中文摘要 II
誌謝 III
LIST OF FIGURES VI
LIST OF TABLES VIII
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 2
CHAPTER 2 FUNDAMENTAL OF ANALOG-TO-DIGITAL CONVERTER 3
2.1 Introduction 3
2.2 The concept of A/D converters 3
2.3 Static Specifications 5
2.3.1 Offset error 6
2.3.2 Gain error 7
2.3.3 Differential Non-Linearity Error (DNL) 8
2.3.4 Integral Non-Linearity Error (INL) 9
2.4 Dynamic Specifications 10
2.4.1 Signal-to-Noise Ratio (SNR) 11
2.4.2 Spurious Free Dynamic Range (SFDR)[2] 12
2.4.3 Signal-to-Noise and Distortion Ratio (SNDR) 13
2.4.4 Effective Number of Bits (ENOB) 14
2.4.5 Dynamic Range (DR) 14
CHAPTER 3 THE SYSTEM OF PIPELINED ANALOG-TO-DIGITAL
CONVERTER 15
3.1 Introduction 15
3.2 Conventional Pipelined ADC 16
3.2.1 Sample-and-Hold Circuit 17
3.3 1.5 Bit/Stage Architecture [2] 18
3.4 Timing Control of Switches 22
CHAPTER 4 LOW-VOLTAGE BULIDING BLOCKS 23
4.1 Introduction 23
4.2 Some Proposed Low Voltage Techniques 25
4.2.1 Bootstrapped MOS Switch 25
4.2.2 Switched-Opamp Technique 27
4.3 Opamp-Reset Switching Technique 30
CHAPTER 5 THE DESIGN OF AN OPAMP-RESET WITH LOADING-FREE
V
ARCHITECTURE PIPELINED A/D CONVERTER 33
5.1 Introduction 33
5.2 The Concept of the Loading-Free Architecture 34
5.3 Fully Differential ORST 36
5.3.1 Pseudo Differential ORST 36
5.3.2 Fully Differential ORST 37
5.4 The Design of the Fully differential ORST MDAC Merged with
Loading-Free Architecture 40
5.4.1 Sub-ADC 42
5.4.1.1 Fully Differential Low-Voltage Comparator 43
5.4.1.2 Simulation Result 47
5.4.2 Low-Voltage Input Sampling Circuit 49
5.4.2.1 Passive Track-And-Reset Circuit 49
5.4.2.2 Simulation Result 50
5.4.3 The Operational Amplifier 51
5.4.3.1 Gain requirement of the Opamp in the design [5] 51
5.4.3.2 Speed requirement of the opamp in the design 52
5.4.3.3 The Schematic of the Opamp 54
5.4.3.4 Common-mode Feedback Circuit 56
5.4 The Simulation of the Pipelined ADC 57
CHAPTER 6 CONCLUSION 60
6.1 Conclusion 60
6.2 Suggestion for Future Work 60
REFERENCES 62
[1] M. Waltari and K. Halonen, “1-V, 9-Bit, Pipelined Switched-Opamp ADC,” IEEE
J. Solid-State Circuits, vol. 36, pp. 129–134, Jan. 2001.
[2] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline
Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606,
May 1999.
[3] D. Y. Chang and U. K. Moon, “A 1.4-V, 10-bit, 25-MS/s Pipelined ADC Using
Opamp-Reset Switching Technique,” IEEE J. Solid-State Circuits, vol. 38, pp.
1401-1404, Aug. 2003.
[4] P. Y. Wu, S. L. Cheung, and H. C. Luong, “A 1-V, 100-MS/s, 8-bit CMOS
Switched-Opamp Pipelined ADC Using Loading-Free Architecture,” IEEE J.
Solid-State Circuits, vol. 42, no. 4, pp. 730 – 738, April 2007.
[5] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and
Simulation, IEEE Press, 1997.
[6] M. Gustavsson, J. J. Wikner, and N. N. Tan, CMOS Data Converters for
Communication, Kluwer, 2000.
[7] J. Li, G. C. Ahn, D. Y. Chang, and U. K. Moon, “A 0.9-V, 12-mW, 5-MSPS
Algorithmic ADC with 77-dB SFDR,” IEEE J. Solid-State Circuits, vol. 40, pp.
960-969, April 2005.
[8] D. Y. Chang, G. C. Ahn and U. Moon, “Sub-1-v Design Techniques for
High-Linearity Multistage/Pipelined Analog-to-Digital Converters,” IEEE
Transactions on Circuits and Systems I, vol. 52, pp. 1-12, Jan. 2005
[9] R. Lotfi, T. S. Mohammad, M. Y. Azizi and O. Shoaei, “Low-Power Design
Techniques for Low-Voltage Fast-Settling Operational Amplifiers in
Switched-Capacitor Application,”, VLSI Journal Integration, vol. 36, no. 4, pp.
175-189, Nov. 2003,
[10] J. Carnes, G. C. Ahn and U. K. Moon, “A 1V, 10b, 60MS/s Hybrid
Opamp-Reset/Switched-RC Pipelined ADC,” IEEE Asian Solid-State Circuits
Conference, pp. 236 – 239, 12-14 Nov. 2007.
[11] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R.
Viswanathan, “A 10-b, 20-Msample/s Analog-to-Digital Converter,” IEEE J.
Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992.
[12] S. H. Lewis, and P. R. Gray, “A Pipelined, 5-Msample/s, 9-bit Analog-to-Digital
Converter,” IEEE J. Solid-State Circuits, vol. sc-22, pp. 954–961, Dec. 1987.
[13] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
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