臺灣博碩士論文加值系統

本論文提出一可用來估測類比數位轉換器之測試激勵訊號誤差量的方法。此估測激勵訊號誤差量的方法是基於統計與連續漸進的概念所發展，藉由提供均勻隨機分佈的測試圖樣給類比數位轉換器，並推導類比數位轉換器的類比輸入端與數位輸出端之片段線性的關係，發展估測測試激勵訊號誤差量之方法。此估測誤差量之方法不但減少了運算的複雜度且經由實驗證明此方法不僅有效且相當精準，因而能提供正確的激勵訊號資訊於類比數位轉換器測試或是內建自我測試的應用上。

This work presents a novel error estimation method of test stimulus for analog to digital converters testing. The error estimation method of test stimulus is based on a statistical successive approximation approach. By applying random patterns with a uniform distribution to ADC, we simplify the piecewise linear relationship between the input and output of the ADC and derive the equations describe the error of test stimulus. The proposed method not only reduces the computational complexity but provides effective and accurate information of test stimulus in developing an ADC testing scheme or BIST methodology.

中文摘要 ……………………………………………………………… i
英文摘要 ……………………………………………………………… ii
誌謝 ……………………………………………………………… iii
目錄 ……………………………………………………………… iv
圖目錄 ……………………………………………………………… v
表目錄 ……………………………………………………………… vi
第一章 緒論………………………………………………………… 1
1-1 研究背景…………………………………………………… 1
1-2 研究動機…………………………………………………… 2
1-3 相關研究…………………………………………………… 3
1-3 論文簡介…………………………………………………… 4
第二章 片段線性行為概述………………………………………… 6
2.1 ADC與DAC的片段線性行為………………………………… 6
2.2 利用內插法來連續近似計算碼邊緣……………………… 10
第三章 以均勻分佈為輸入訊號之片段線性關係………………… 13
3.1 片段線性行為……………………………………………… 13
3.2 測試激勵訊號估測方法…………………………………… 16
第四章 遺失碼之修正……………………………………………… 20
4.1 遺失碼之種類……………………………………………… 20
4.2 遺失碼之影響……………………………………………… 21
4.3 變動量之修正……………………………………………… 27
第五章 實驗結果…………………………………………………… 29
第六章 結論…………………………………………………………… 35
參考文獻 ………………………………………………………………… 36

[1]M. G. C. Flores, M. Negreiros, L. Carro, A. A. Susin, “INL and DNL estimation based on noise for ADC test,” Proc. IEEE Trans. on Instrumentation and Measurement, pp. 1391-1395, 2004.
[2]R. Holcer, L. Michaeli, J. Saliga, “DNL ADC Testing by the Exponential Shaped Voltage,” Proc. IEEE Trans. on Instrumentation and Measurement, pp. 946-949, 2003.
[3]M. Burns, G.W. Robert, “An Introduction to Mixed- Signal IC Test and Measurement,” Oxford University Press, 2001.
[4]D. A. Johns, k. Martin, “Analog Integrated Circuit Design,” John Wiley & Sons: New York, 1997.
[5]Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design,” OXFORD. New York, 2002.
[6]S. Cherubal, A. Chatterjee, “Optimal INL/DNL Testing of A/D Converters Using a Linear Model,” Proc. IEEE Int’l Test Conf., pp. 358-366, 2000.
[7]F. Azais, S. Bernard, Y. Bertrand, M. Renovell, “Towards and ADC BIST Scheme using the Histogram Test Technique,” Proc. European Test Workshop, pp. 129-134, 2000.
[8]M. Renovell, F. Azais, S. Bernard, Y. Bertrand, “Hardware Resource Minimization for a Histogram-Based ADC BIST,” Proc. VLSI Test Symposium, pp. 247-252, 2000.
[9]A. Frish, T. Almy, “HABIST: Histogram-based Analog Built-In Seft-Test,” Proc. International Test Conference, pp. 760-767, 1997.
[10]S. Max, “Testing High Speed High Accuracy Analog to Digital Converters Embedded in Systems on a Chip,” Proc. IEEE Int’l Test Conf., pp. 763-771, 1999.
[11]J. L. Huang, C. K. Ong, K. T. Cheng, “A BIST Scheme for On-Chip ADC and DAC Testing,” Proc. IEEE Design Automation & Test in Europ., pp. 216-220, 2000.
[12]M. J. Ohletz, “Hybrid Built-In Self-Test(HBIST) for Mixed Analogue/Digital Integrated Circuits,” Proc. European Test Conference, pp. 307-316, 1991.
[13]R. de Vries, T. Zwemstra, E. Bruls, P. Regtien, ”Built-In Self-Test Methodology for A/D Converters,” Proc. European Design and Test Conference, pp. 353-358, 1997.
[14]M. G. C. Flores, M. Negreiros, A. A. Susin, “A Noise Generator for Analog-to-Digital Converter Testing,” Proc. Symp. on Integrated Circuits and Systems Design, pp. 135-140, 2002.
[15]K. Arabi, B. Kaminska, “Efficient and Accurate Testing of Analog to Digital Converters Using Oscillation test Method,” Proc. IEEE Europ. Design & Test Conf., pp. 348-352, 1997.
[16]K. Arabi, B. Kaminska, “Oscillation Built-In Self-Test(OBIST) scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits,” Proc. International Test Conference, pp. 786-795, 1997.
[17]J.W. Lin, C.L. Lee, J.E Chen, “A Statistical Successive Approximation Approach for DAC/ADC Code Edge Estimation,” Proc. IEEE European Test Workshop, pp.359-363, 2002.