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[1]I. Yamaguchi, F. Matsumoto and Y. Noguchi, “Technique to improve linearity of transconductor with bias offset voltages controlling a tail current,” Electronics Letters, vol. 41, no. 2, pp. 825-828, Oct. 2005. [2]Susanta Sengupta, “Adaptively biased linear transconductor,” IEEE Trans. on Circuits and Systems-I, vol. 52, no. 11, pp. 2369-2375, Nov. 2005. [3]Chutham Sawigun and Jirayuth Mahattanakul, “A compact high current efficiency low-voltage MOS transconductor with nearly constant input voltage range,” IEEE International Symposium on Circuits and Systems, pp. 221-224, May 2007. [4]Chutham Sawigun and Jirayuth Mahattanakul, “A low-voltage CMOS linear transconductor suitable for analog multiplier application,” IEEE International Symposium on Circuits and Systems, pp. 1543-1546, May 2006. [5]Bahram Fotouhi, “All-MOS voltage-to-current converter,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 147-151, January 2001. [6]Yun-Che Wen and Kuen-Jong Lee, “A current-mode BIST structure of DACs,” Journal of the International Measurement Confederation, vol. 31, no. 3, pp. 147-163, April 2002. [7]Ayman A. Fayed and Mohammed Ismail, “A low-voltage, highly linear voltage-controlled transconductor,” IEEE Trans. on Circuits and Systems-II, vol. 52, no. 12, pp. 831-835, Dec. 2005. [8]Roger Yubtzuan Chen, Seng-Fong Lin, and Ming-Shian Wu, “A linear CMOS voltage-to-current converter ,” Circuits, Systems, and Signal Processing, vol. 25, no. 4, pp. 497-509, 2006. [9]Il-Song Han, “A novel tunable transconductance amplifier based on voltage-controlled resistance by MOS transistors,” IEEE Trans. on Circuits and Systems-II, vol. 53, no. 8, pp. 662-666, August 2006. [10]Tien-Yu Lo and Chung-Chih Hung, “1-V linear CMOS transconductor with -65dB THD in nano-scale CMOS technology,” IEEE International Symposium on Circuits and Systems, pp. 3792-3795, May 2007. [11]Charles G. Sodini, Ping-Keung Ko and John L. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. on Electron Devices, vol. ED-30, no. 10, pp. 1386-1393, Oct. 1984. [12]Mozhgan Mansuri and Chih-Kong Ken Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003. [13]R. Raut, “A novel VTC for analog IC applications,” IEEE Trans. on Circuits and Systems-II, vol. 39, no. 12, pp. 882-883, Dec. 1992. [14]J. Galan, R. G. Carvajal, A. Torralba, F. Munoz, and J. Ramirez-Angulo, “A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range,” IEEE Trans. on Circuits and Systems-I, vol. 52, no. 2, pp. 283-291, February 2005. [15]The BSIM model, BSIM Research Group at UC Berkeley. Available: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html [16]Behzad Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw Hill, 2001. [17]Chun Wei Lin, "Constant current source with threshold voltage and channel length modulation compensation," US Patent No:7015846.
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