跳到主要內容

臺灣博碩士論文加值系統

(18.97.9.172) 您好!臺灣時間:2025/02/14 04:32
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:黃宥脀
研究生(外文):You-Cheng Huang
論文名稱:具補償遷移率退化及臨界電壓之高線性度電壓電流轉換器
論文名稱(外文):An Ultra-Linear Voltage-To-Current Converter with Mobility Degradation and Threshold-Voltage Compensations
指導教授:林俊偉林俊偉引用關係
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:47
中文關鍵詞:電壓電流轉換器轉導放大器遷移率退化
外文關鍵詞:mobility degradationtransconductorvoltage-to-current converter
相關次數:
  • 被引用被引用:0
  • 點閱點閱:347
  • 評分評分:
  • 下載下載:34
  • 收藏至我的研究室書目清單書目收藏:0
此篇論文提出了一具補償遷移率退化及臨界電壓之高線性度電壓電流轉換器。對於在深次微米CMOS製程中之遷移率退化效應,於此所提出的補償方法可以有效的減少電壓與電流關係中之高階非線性項。此外,藉由修改電流源之結構,所提出之設計具有對臨界電壓變動之不敏感性且產生較高之電源拒斥比。根據實驗結果,在3.3V的CMOS製程下可以達到0.9V的工作範圍以及幾乎為固定轉導之正規化數值,其範圍為0.946~1.025。此外,實驗結果也顯示出所提出之設計可將臨界電壓變動所產生之變動誤差降至3%。本作品完整地推導所提出之理論發展與設計流程且使用TSMC 0.35um 2P4M 3.3V CMOS 製程予以實現。
This work presents a design of ultra-linear voltage-to-current converter with mobility degradation and threshold-voltage compensations. For mobility degradation in deep submicron processes, the proposed compensation method can effectively decrease the high order nonlinear items within relationship between voltage and current. In addition, through modifying the configuration of current source, the proposed design is insensitive to variation of threshold voltage and also leads to higher power rejection ratio. According to experiment results, we enable a wide operational range and almost constant transconductance that reach to 0.9V and 0.946~1.025 normalized value in 3.3V COMS process respectively. Moreover, the experiment result also shows the proposed design can decrease the variation error less than 3% caused by variation of threshold-voltage which under 3%. The theoretical development and design flow of proposed method are derived completely and this work is implemented by TSMC 0.35um 2P4M 3.3V CMOS process.
中文摘要 ………………………………………………………… i
英文摘要 ………………………………………………………… ii
誌謝 ………………………………………………………… iii
目錄 ………………………………………………………… iv
圖目錄 ………………………………………………………… v
表目錄 ………………………………………………………… vi
第一章 緒論…………………………………………………………… 1
1.1 研究背景……………………………………………………… 1
1.2 研究動機……………………………………………………… 2
1.3 相關研究……………………………………………………… 3
1.4 論文架構……………………………………………………… 6
第二章 遷移率退化效應與電路理論發展…………………………… 7
2.1 遷移率退化效應……………………………………………… 7
2.2 遷移率退化因子與閘極、汲極、源極電壓及電晶體尺寸
關係…………………………………………………………… 10
2.3 創新電壓電流轉換器基本設計概念與理論推導…………… 14
2.4 電路之設計規範……………………………………………… 19
2.5 臨界電壓補償技術…………………………………………… 25
第三章 電路實現與佈局……………………………………………… 27
第四章 佈局後模擬結果與比較……………………………………… 31
第五章 結論…………………………………………………………… 37
參考文獻 ………………………………………………………………… 38
[1]I. Yamaguchi, F. Matsumoto and Y. Noguchi, “Technique to improve linearity of transconductor with bias offset voltages controlling a tail current,” Electronics Letters, vol. 41, no. 2, pp. 825-828, Oct. 2005.
[2]Susanta Sengupta, “Adaptively biased linear transconductor,” IEEE Trans. on Circuits and Systems-I, vol. 52, no. 11, pp. 2369-2375, Nov. 2005.
[3]Chutham Sawigun and Jirayuth Mahattanakul, “A compact high current efficiency low-voltage MOS transconductor with nearly constant input voltage range,” IEEE International Symposium on Circuits and Systems, pp. 221-224, May 2007.
[4]Chutham Sawigun and Jirayuth Mahattanakul, “A low-voltage CMOS linear transconductor suitable for analog multiplier application,” IEEE International Symposium on Circuits and Systems, pp. 1543-1546, May 2006.
[5]Bahram Fotouhi, “All-MOS voltage-to-current converter,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 147-151, January 2001.
[6]Yun-Che Wen and Kuen-Jong Lee, “A current-mode BIST structure of DACs,” Journal of the International Measurement Confederation, vol. 31, no. 3, pp. 147-163, April 2002.
[7]Ayman A. Fayed and Mohammed Ismail, “A low-voltage, highly linear voltage-controlled transconductor,” IEEE Trans. on Circuits and Systems-II, vol. 52, no. 12, pp. 831-835, Dec. 2005.
[8]Roger Yubtzuan Chen, Seng-Fong Lin, and Ming-Shian Wu, “A linear CMOS voltage-to-current converter ,” Circuits, Systems, and Signal Processing, vol. 25, no. 4, pp. 497-509, 2006.
[9]Il-Song Han, “A novel tunable transconductance amplifier based on voltage-controlled resistance by MOS transistors,” IEEE Trans. on Circuits and Systems-II, vol. 53, no. 8, pp. 662-666, August 2006.
[10]Tien-Yu Lo and Chung-Chih Hung, “1-V linear CMOS transconductor with -65dB THD in nano-scale CMOS technology,” IEEE International Symposium on Circuits and Systems, pp. 3792-3795, May 2007.
[11]Charles G. Sodini, Ping-Keung Ko and John L. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. on Electron Devices, vol. ED-30, no. 10, pp. 1386-1393, Oct. 1984.
[12]Mozhgan Mansuri and Chih-Kong Ken Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003.
[13]R. Raut, “A novel VTC for analog IC applications,” IEEE Trans. on Circuits and Systems-II, vol. 39, no. 12, pp. 882-883, Dec. 1992.
[14]J. Galan, R. G. Carvajal, A. Torralba, F. Munoz, and J. Ramirez-Angulo, “A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range,” IEEE Trans. on Circuits and Systems-I, vol. 52, no. 2, pp. 283-291, February 2005.
[15]The BSIM model, BSIM Research Group at UC Berkeley. Available: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
[16]Behzad Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw Hill, 2001.
[17]Chun Wei Lin, "Constant current source with threshold voltage and channel length modulation compensation," US Patent No:7015846.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top