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研究生:詹慶達
研究生(外文):Ching-Da Chan
論文名稱:低成本及閘架構之最小和演算法低密度奇偶校驗碼解碼器
論文名稱(外文):Low Cost Low-density Parity-Check Decoder Using AND Gate Based Min-Sum Algorithm
指導教授:楊博惠
指導教授(外文):Po-Hui Yang
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:74
中文關鍵詞:最小和演算法錯誤更正碼疏查核碼通訊晶片解碼器
外文關鍵詞:LDPCMin-sum algorithmECCdecoder
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  • 被引用被引用:1
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本論文提出一種在不影響解碼效能下用簡單邏輯及閘架構全平行LDPC解碼器架構。我們先提出及閘架構MSA,依據所提出的演算法,可以將其解碼器的Check Node Unit(CNU)複雜度大幅降低,在及閘架構MSA中,我們在Variable-to-Check node message做不規則量化,經過不規則量化的數值使用邏輯及閘取代在傳統MSA裡CNU所需要使用到的比較器,以減少硬體複雜度及硬體面積。實現在IEEE 802.16e standard 奇偶校驗矩陣(576, 288),在TSMC 0.18μm製程下與傳統MSA LDPC解碼器約可省22%,與實現在IEEE 802.11n standard 奇偶校驗矩陣(648, 324),在TSMC 0.13μm製程下與傳統MSA LDPC解碼器約可省30%,沒有管線的架構速度可達100MHz。本研究並應用在MIMO系統中的LDPC解碼器,採用IEEE 802.16e standard 奇偶校驗矩陣(576, 288),實現在TSMC 0.18μm製程下,core size為2800μm x 2800μm。
In this thesis we proposed a new full parallel LDPC decoder, using the simple AND gates on check-node circuit operation, resulting no bit-error-rate performances lose when compare with the original min-sum algorithm. A modified min-sum algorithm is derived firstly, and then the hardware complexity of the check-node unit is reduced tremendously. Meanwhile, the variable-to-check node message has mapped into a special irregular quantization method in order that we can just employ basic AND gates to replace the complex comparators in check-node unit. In the hardware implementation case of IEEE 802.16e standard, LDPC matrix scale setting as (576, 288) and under the 0.18μm IC technology, new proposed LDPC decoder saves 22% hardware area. Furthermore, the implemented IEEE 802.11n with matrix scale (648, 324) and taking 0.13μm process technology, it saves 30% hardware when comparing with the traditional min-sum architecture. The operational speed can reach up to 100MHz without pipelining. A real MIMO application implementation is completed, in this thesis, adopting IEEE 802.16e standard matrix scale (576, 288) under a 0.18μm technology, and the core size of LDPC decoder is only 2800μm × 2800μm.
摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究背景 1
1.2 研究方法與目的 2
1.3 論文架構 3
第二章 低密度奇偶校驗碼介紹 4
2.1 低密度奇偶校驗碼基本概念 4
2.1.1 線性區塊碼 4
2.1.2 低密度奇偶校驗碼 5
2.1.3 Tanner Graph 6
2.1.4 低密度奇偶校驗碼編碼 8
2.2 低密度奇偶校驗碼解碼演算法 11
2.2.1 Sum-Product 演算法 12
2.2.2 Log-Domain Sum-Product Algorithm (Log-SPA) 16
2.2.3 Min-Sum Algorithm 22
2.2.4 Normalized Min-Sum Algorithm與Offset Min-Sum Algorithm 26
2.3 演算法分析比較 28
第三章 新型精簡硬體之簡化Min-Sum演算法 30
3.1 傳統Min-Sum演算法瓶頸 31
3.2 以簡單邏輯及閘運算簡化Min-Sum演算法 32
3.3 效能分析比較 34
第四章 低成本及閘架構奇偶校驗碼解碼器 42
4.1傳統架構之硬體複雜度問題 42
4.2及閘運算之低密度奇偶校驗碼解碼器 43
4.2.1 AND Operation Check Node Unit(ACNU)架構 44
4.2.2 含不規則量化表之Variable Node Unit架構 47
4.3 新架構與傳統架構之效能分析比較 49
第五章 含自我測試電路LDPC解碼器硬體實現 52
5.1 含自我測試電路解碼器整體架構 52
5.2 ASIC實現流程 56
5.2.1 Matlab model模擬 56
5.2.2 RTL Coding與模擬 57
5.2.2 Synthesis與驗證 58
5.2.3 DFT & ATPG 58
5.2.4 Place and Route 59
5.2.5 DRC & LVS 60
5.2.6 Post-layout Gate-level Simulation 60
第六章 結論 61
參考文獻 62
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