臺灣博碩士論文加值系統

本論文提出兩種振盪器架構，分別採用雙閘耦合技術之差動壓控振盪器與採用自動轉導匹配技術之電流再利用振盪器，設計於第四代行動通訊與WiMAX 頻帶之寬頻應用。在採用雙閘耦合技術的差動壓控振盪器方面，同時耦合電晶體閘極與基體，使等效轉導增大而降低?率消耗，並使用差動壓控壓抑共模雜訊。0.18-μm CMOS 振盪器晶片量測結果顯示，振盪頻率範圍為3.02 – 3.89 GHz，輸出?率為-4.1 dBm，於3.02 GHz 時，相位雜訊為-93 dBc/Hz@1 MHz offset，消耗必v為6 mW，優化指數(FOM)為-156.1。在採用自動轉導匹配技術的振盪器方面，將CMOS center-tapped（中央抽頭式）電感之訊號回授至交互耦合電晶體之源極退化電阻，使PMOS 與NMOS 之轉導值自動匹配而平衡振幅輸出。量測結果，振盪頻率範圍為2.93 – 3.62 GHz，輸出?率為-4.3 dBm，於2.93 GHz 時，相位雜訊為-112.8 dBc@1 MHz offset，輸出?率不平衡度於全頻段中約為8-9 %，?率消耗為1.95 mW，優化指數(FOM)為-179.4。

Two novel voltage-controlled oscillators (VCOs) are designed for the
fourth-generation and WiMAX applications, which are the differential VCO with
double-gate coupling (DGC-VCO) technique and the current-reused VCO with
auto-transconductance matching (ATM-VCO). In DGC-VCO, the gate and bulk of
transistor are coupled simultaneously for greater transconductance, leading to lower
power consumption. The VCO is implemented with 0.18-μm CMOS technology. The
measured tuning range is 3.02 to 3.89 GHz and the phase noise is -93 dBc/Hz at
1MHz offset from 3.02 GHz. The single-ended output power is -4.1 dBm with 6 mW
power consumption in VCO core. The figure of merit is -156.1 For ATM-VCO, the
signal, which is center-tapped from the tank inductor, is fed to the source degeneration
resistor such that the transconductances of PMOS and NMOS are automatically
matched. Therefore, the amplitude imbalance can be dramatically improved. The
measured tuning range is 2.93 to 3.62 GHz, where the amplitude imbalance is 8-9% .
The phase noise is -112.8 dBc/Hz at 1MHz offset from 2.93 GHz. The output power is
-4.3 dBm with 1.95 mW power consumption in VCO core. The figure of merit is
-179.4.

第一章 序論.................................................................................................................1
1.1 研究背景與動機..........................................................................................1
1.2 寬頻壓控振盪器..........................................................................................1
1.3 論文架構......................................................................................................2
第二章 CMOS VCO 相位雜訊分析.........................................................................3
2.1 相位雜訊來源..............................................................................................3
(a) 熱雜訊....................................................................................................3
(b) 射彈雜訊................................................................................................3
(c) 閃爍雜訊................................................................................................3
2.2 相位雜訊頻譜..............................................................................................5
2.3 相位雜訊效應..............................................................................................7
2.4 壓抑相位雜訊..............................................................................................8
(a) 使用P 型通道元件...............................................................................8
(b) 使用電容性交互耦合............................................................................9
(c) 使用2nd-harmonic filter.........................................................................9
(d) 採用P-N 互補對稱式電路設計.........................................................10
(e) 源極退化電阻技術..............................................................................10
(f) 差動壓控機制......................................................................................11
(g) 將負阻電路偏壓在電壓權限與電流權限區之間..............................11
(h) 高次諧波共振腔..................................................................................12
(i) 振盪器環型耦合陣列..........................................................................13
(j) 切換式MOS 偏壓...............................................................................14
(k) 使用高Q 值諧振元件.........................................................................15
第三章 對稱尺寸之差動壓控雙閘耦合振盪器......................................................16
3.1 降低相位雜訊方法之優缺點....................................................................16
3.2 雙閘耦合技術............................................................................................16
3.3 對稱最佳尺寸設計....................................................................................18
3.4 差動壓控....................................................................................................21
(a) 小訊號分析..........................................................................................21
(b) 大訊號分析..........................................................................................23
3.5 模擬與量測結果........................................................................................25
第四章 自動轉導匹配之電流再利用振盪器..........................................................29
II
4.1 現有文獻之電流再利用振盪器................................................................29
4.2 自動轉導匹配技術....................................................................................30
4.3 模擬與量測結果........................................................................................34
第五章 結論...............................................................................................................40
附錄一 二次諧波耦合四相位振盪器.......................................................................41
A1.1 四相位振盪器耦合方式............................................................................41
(a) 並聯耦合..............................................................................................41
(b) 串聯耦合..............................................................................................42
(c) 基體耦合..............................................................................................42
(d) 源極退化耦合......................................................................................42
(e) 變壓器耦合..........................................................................................42
(f) 電流源直接交互耦合..........................................................................43
(g) 電流源基體交互耦合..........................................................................43
(h) 二倍頻注入鎖定..................................................................................43
A1.2 二次諧波電容耦合....................................................................................43
A1.3 模擬結果....................................................................................................46
參考文獻......................................................................................................................49

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