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研究生:梁明鈞
研究生(外文):Ming-Chun Liang
論文名稱:採用快速傅利葉處理器之管線式類比數位轉換器校正方法
論文名稱(外文):A Fast-Fourier-Transform-Based Calibration Methodfor Pipeline ADC
指導教授:李顺裕
指導教授(外文):Shuenn-Yuh Lee
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:中文
論文頁數:72
中文關鍵詞:管線式類比數位轉換器校正技術
外文關鍵詞:pipeline ADCcalibration method
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本論文提出一種採用快速傅利葉處理器之類比數位轉換器校正方法,此種校正方式可克服電容之不匹配及運算放大器之有限開迴路增益,而電容之不匹配及運算放大器之有限增益會使得每一級之放大倍率並不恰好等於2n,這裡使用了快速傅利葉處理器求出各級實際之乘數並且利用數位方法產生新的數位輸出。由於此校正方法可克服運算放大器之有限開迴路增益,因此在類比數位轉換器之設計上,運算放大器開迴路增益之規格便不會那麼嚴苛,便可設計開迴路增益較小的運算放大器以減少必v消耗。由12-bit之管線式類比數位轉換器行為模型之模擬結果得知,在1%之電容不匹配下,其校正後之SNDR可提高約17.4dB,且其ENOB之變異度亦從0.417-bit將低至0.077-bit。
此類比數位轉換器使用標準TSMC 0.18um 1P6M Mixed Signal Process實現。由佈局後之模擬結果得知,在操作電壓為1.8伏,取樣頻率為100百萬赫茲下,訊號與雜訊失真比為57.14dB,有效位元為9.2-bit,此類比數位轉換器之總必v為70mW。
This study presents a Fast-Fourier-Transform- Based (FFT-based) digital calibration method for multistage pipeline analog-to-digital converter (ADC). The calibration method can overcome the capacitor mismatch and finite gain of operation amplifier (OPAMP). Because the capacitor mismatch and finite opamp gain would let the radix of all the stages not equal to 2n, the FFT processor can be adopted to evaluate the real radixes of all the stages and generate new digital output to compensate the error caused by nonideal circuits. Moreover, due to the finite gain of OPAMP can be compensated, the specification of the OPAMP gain is not so critical. That is, the low-gain opamp can be implemented to reduce the power dissipation of the pipeline ADC. For the 12-bit ADC, the simulation result reveal the signal-to-noise-and-distortion ratio (SNDR) can be improved beyond 17.4 dB and the variance of effective number of bit (ENOB) can be decreased from 0.417 bits to 0.077 bits.
This pipelined ADC is implemented in standard TSMC 0.18um 1P6M Mixed Signal Process technology. The post simulation results show the SNDR is 57.14dB, and the ENOB is 9.2-bit with 1.8V of the power supply and 100MS/s of the sampling rate. The total pipelined ADC power dissipation is about 70mW.
摘要 I
Abstract II
誌謝 IV
圖目錄 VII
第一章 緒論 1
1.1 動機 1
1.2 論文架構 2
第二章 類比數位轉換器之架構與簡介 3
2.1 類比數位轉換器簡介 3
2.1.1 解析度(Resolution)及最小有效位元(Least Significant Bit, LSB) 3
2.1.2 輸入範圍(Input Range) 3
2.1.3 訊號雜訊比(Signal-to-Noise Ratio, SNR) 3
2.1.4 訊號雜訊失真比(Signal-to-Noise and Distortion Ratio, SNDR) 5
2.1.5 有效位元(Effective Number of Bit, ENOB) 5
2.1.6 微分非線性誤差(Differential Nonlinearity, DNL) 5
2.1.7 積分非線性誤差(Integral Nonlinearity, INL) 6
2.2類比數位轉換器之架構 6
2.2.1 快閃式類比數位轉換器(Flash ADC) 6
2.2.2 兩階段式類比數位轉換器(Two-Step ADC) 7
2.2.3 管線式類比數位轉換器(Pipeline ADC) 8
2.2.4 運算式類比數位轉換器(Algorithmic ADC) 9
2.2.5 分時並行式類比數位轉換器(Time-Interleaved ADC) 10
2.3 管線式類比數位轉換器之簡介 11
2.4 1.5-bit/stage之管線式類比數位轉換器 13
第三章 管線式類比數位轉換器之校正技術 17
3.1 管線式類比數位轉換器之非理想效應 17
3.2採用快速傅利葉處理器之校正技術 19
3.2.1 誤差與諧波之關係 20
3.2.2 數位校正技術 23
4.1 取樣保持電路 34
4.1.1 開關 34
4.1.2 運算放大器之規格 38
4.1.3 運算放大器之架構 41
4.1.4 偏壓電路 44
4.1.6 時脈產生電路 46
4.1.7 取樣保持電路 47
4.2 MDAC 49
4.3 Sub-ADC 50
4.3.1 動態比較器(Dynamic Comparator) 50
4.3.2 1.5-bit/stage sub-ADC 51
4.3.3 2-bit Flash ADC 52
4.4 移位暫存器 52
4.5 運算放大器共用(OPAmp Sharing)及依比例下降(Scaling)技術 53
4.5.1 運算放大器共用(OPAmp Sharing) 53
4.5.2 依比例下降(Scaling) 56
4.6快速傅利葉處理器及浮點數乘加器 56
4.6.1 快速傅利葉處理器(FFT Processor) 57
4.6.2 浮點數乘加器 59
4.7 管線式類比數位轉換器模擬結果 61
4.8 效能比較 64
第五章 量測結果 66
5.1 測試步驟及考量 66
5.2 量測結果 67
第六章 結論與未來展望 69
參考文獻 70
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