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研究生:賴欣怡
研究生(外文):Hsin Yi Lai
論文名稱:在多處理器架構上利用動態電壓調整模組來執行串流運算
論文名稱(外文):DVS Modeling for Streaming Applications Running on a Multiprocessor Architecture
指導教授:謝萬雲謝萬雲引用關係
指導教授(外文):W. Y. Shieh
學位類別:碩士
校院名稱:長庚大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
論文頁數:86
中文關鍵詞:多處理器管線串流式應用動態電壓調整
外文關鍵詞:multi-processorspipelinestreaming applicationDVS
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諸多嵌入式或行動裝置都支援多媒體影音功能,而這些功能都強調串流式資料運算的效能需求。為了滿足上述應用服務效能需求,處理器的架構也不斷地推陳出新。多處理器(Multi-processors) 即是提高效能的新趨勢之一。
本研究將設計低電耗機制的多處理器及shared-memory架構來節省處理資料及傳輸資料時所需的電耗。我們把多處理器視為一條運算管線,一個處理器就如同一個pipe-stage。我們假設每個處理器皆提供雙重電壓/頻率,其運算速度(頻率)與其供應電壓成正比。由於streaming data在管線中每一個處理器的工作量不一定均等,因此將透過程式執行時的即時計算來預估每一個處理器可容許工作的時間。在不影響系統效能的條件限制下,如果預估時間大於使用原始電壓/頻率執行的工作時間,此處理器便可用較低之供應電壓/頻率來執行運算。反之,則以較高電壓/頻率全速執行。如此可使多處理器在運算串流式資料時,能在不影響產能的情況下節省電耗。
實驗中將使用HyperLAN2應用程式來評估我們設計的方法。評估節省電耗的標準包括理想的預估值及透過實驗模擬的結果值。結果顯示在3-processors的微處理器架構下,(假設資料輸入時間為1 us的速度下),各模型計算節省電耗的理想預估值為最低68.23(%)到最高81.11(%),透過實驗模擬結果省下的電耗值為最低65.12(%)到最高81.11(%)。差異在0%到5%之間。
Most modern embedded or mobile devices support multimedia applications. Most of them support streaming data operations. To satisfy performance requirements for streaming operations, the multi-processor architecture has been applied to modern processor design.
One big problem to design such processor is its power consumption. In this thesis, we will design a dynamic voltage scaling mechanism for multi-processor and shared-memory architecture to save the energy consumption when processing streaming data and transmitting data. In our design, we consider that the processing units in a multi-processor are connected as a pipeline datapath, just like the function units in the pipeline. We also assume that each processing unit can work in two supplied voltage/frequency levels. Because the streaming operations on each processor may cause unbalanced workloads, we will dynamic predict the operation time which can be toleranced for execution on each processor. If a processor has a longer predicted operation time than the time executed by current voltage level, it can then use lower frequency and supply voltage to execute that operation and thus save power consumption. Otherwise, a processor should have a higher supply voltage to speedup the execution such that the deadline requirement can be met.
We use the HyperLAN2 program to evaluate our design. We evaluate the ideal percentages of power saving by applying our design on a multi-processor system, for three processors, input data time is 1us, the power saving is from 68.23(%) to 81.11(%). For the same condition, the simulation result show the percentages of power saving is from 65.12(%) to 81.11(%). The division of power saving is from 0% to 5%.
目錄
指導教授推薦書
口試委員審定書
授權書 iii
誌謝 iv
摘要 v
Abstract vii
目錄 ix
圖目錄 xi
表目錄 xiii
第一章 介紹 1
1.1 背景 1
1.3 設計議題 9
1.4 研究目標 10
1.5 論文結構 12
第二章 相關研究 13
2.1Streaming-program pipelining on multi-processors相關研究 13
2.2 DVS on processor相關研究 14
2.3 DVS for Streaming Application相關研究 15
第三章 研究方法 17
3.1 Notation介紹 19
3.2 shared-memory基本架構的四種節能式管線化運算模型 20
3.2.1 SCSP模型 20
3.2.2 PCSP模型 26
3.2.3 SCPP模型 32
3.2.4 PCPP模型 38
3.2.5電壓/頻率調整模型 44
3.3實作管線化運算模型 44
3.4模型運算及Processor_status_table、Data_table的更新 53
第四章 實驗 55
4.1 實驗方法 55
4.2 實驗結果 57
第五章 結論 69
參考文獻 71

圖目錄

圖1-1. Kavaldjiev et. al.提出之多處理器架構示意圖 3
圖1-2. SCSP資料流程圖 4
圖1-3. PCSP資料流程圖 5
圖1-4. SCPP資料流程圖 6
圖1-5. PCPP資料流程圖 7
圖3-1. 降低頻率延長執行時間 18
圖3-2. SCSP模型示意圖 20
圖3-3. SCSP管線運作示意圖 21
圖3-4. SCSP之例子 23
圖3-5. SCSP之例子 25
圖3-6. PCSP模型示意圖 27
圖3-7. PCSP管線運作示意圖一 28
圖3-8. PCSP管線運作示意圖二 28
圖3-9. PCSP之例子 31
圖3-10. SCPP模型示意圖 33
圖3-11. SCPP管線運作示意圖一 34
圖3-12. SCPP管線運作示意圖二 34
圖3-13. SCPP之例子 37
圖3-14. PCPP模型示意圖 38
圖3-15. PCPP管線運作示意圖一 39
圖3-16. PCPP管線運作示意圖二 40
圖3-17. PCPP之例子 43
圖3-18. Hardware schematic diagram 46
圖3-19. Processor_status_table 47
圖3-20. Data_table 48
圖3-21. DVS controller 50
圖3-22. voltage switching circuit 50
圖3-23. DVS機制系統流程圖 52
圖4-1. HyperLAN2 receiver架構圖 56
圖4-2. HyperLAN2 receiver 之傳輸及運作時間圖 58

表目錄

表3-1. notation 19
表4-1. power model 57
表4-2. processor 實際使用的utilization和throughput 59
表4-3. processor 最大的utilization 60
表4-4. processor utilization中idle所佔的比例 62
表4-5. 各模型的Save power 66
表4-6. 實際模擬程式計算節省的電耗 67
[1] http://www.intel.com/design/network/products/npfamily/index.htm
[2] http://www.cavium.com/OCTEON-Plus_CN58XX.html
[3] Kavaldjiev, N.K. et al.“Throughput of Streaming Applications Running on a Multiprocessor Architecture,” EUROMICRO Symposium on Digital System Design, 2005.
[4] Gang Qu, “What is the limit of energy saving by dynamic voltage scaling?” Proceedings of IEEE/ACM International Conference on Computer Aided Design, 2001 , Page(s):560 – 563.
[5] http://www.eetimes.com/
[6] Ying Tan , Parth Malani , Qinru Qiu , Qing Wu, “Workload prediction and dynamic voltage scaling for MPEG decoding,” Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
[7] Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi, “Joint throughput and energy optimization for pipelined execution of embedded streaming applications,” Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools LCTES '07, June 2007 ACM SIGPLAN Notices
[8] J. A. J. Leiten, et. al, “Stream Communication between Real-Time Tasks in a High Performance Multiprocessor,” Proc. Design Automation and Test in Europe, 1998
[9] Fen Xie, Margaret Martonosi, Sharad Malik “Intraprogram Dynamic Voltage Scaling: Bounding Opportunities with Analytic Modeling” ACM Transactions on Architecture and Code Optimization, Vol. 1, No. 3, September 2004, Pages 1–45.
[10] Seokwoo Lee, et al., “Reducing pipeline energy demands with local DVS and dynamic retiming,” Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Page(s):319 – 324.
[11] ETSI, “Broadband Radio Access Networks (BRAN); HiperLAN type 2; Physical (PHY) Layer,” Technical Specification ETSI TS 101 475 V1.2.2 (2001-02), February 2001.
[12] P.M. Heysters, G.K. Rauwerda and G.J.M. Smit, “Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture,” Proceedings of the 18th International Parallel & Distributed Processing Symposium Reconfigurable Architectures Workshop (RAW 2004), Santa Fé, New Mexico, U.S.A., April 2004, ISBN 0-7695-2132-0.
[13] R. Xu, C. Xi, R. Melhem, and D. Moss. “Practical PACE for
Embedded Systems,” In ACM EmSoft, pp. 54-63, 2004.
[14] L. T. Clark. “Circuit Design of XScale (tm) Microprocessors,” In 2001 Symposium on VLSI Circuits, Short Course on Physical Design for Low-Power and High-Performance Microprocessor Circuits. 2001.
[15] Intel Corp. “Intel XScale (tm) Core Developer’s Manual,” 2002. http://developer.intel.com/design/intelxscale/.
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