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研究生:邱景祥
研究生(外文):Jing Siang Chiu
論文名稱:射頻濺鍍高介電閘極絕緣層在複晶矽薄膜上之特性
論文名稱(外文):Characteristics of High-k Gate Dielectrics by RF sputtering deposited on the polycrystalline silicon
指導教授:高泉豪
指導教授(外文):C. H. Kao
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
論文頁數:101
中文關鍵詞:高介電係數氧化釓五氧化二鉭三氧化二鉺複晶矽薄膜
外文關鍵詞:high-k materialsGd2O3Ta2O5Er2O3polysilicon
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摘要
在論文中,我們研究高介電係數材料氧化釓、五氧化二鉭和三氧化二鉺的特性用來取代傳統二氧化矽氧化層,以便應用於薄膜電晶體製程技術上。我們使用射頻濺鍍機來沉積高介電係數材料,再結合使用後段快速熱退火處理技術來修補高介電係數材料本身以及和複晶矽薄膜之間的缺陷,因而改善複晶矽氧化層電容之特性與品質。
由於在低溫多晶矽薄膜的研究上,複晶矽薄膜仍有著表面粗糙、表面的缺陷密度、複晶矽邊界的缺陷密度…等缺點,因此在複晶矽氧化層電容方面的電性改善包含崩潰電場、缺陷捕捉速率和電荷至崩潰累積電荷。所以我們使用高介電係數材料來製作複晶矽氧化層電容,其具有相當高的介電常數,較低的電流密度,和高崩潰電場及良好的熱穩定度。然後再透過快速熱退火的處理,並且分析其電性及物性結果。我們可以發現經過快速熱退火的處理後,其將會修補晶格之缺陷,大大地改善其電性結果。主要是經過後段快速熱退火處理後,可修補高介電絕緣層內的缺陷以及高介質材料與複晶矽界面間的缺陷能態,同時並形成較好的鍵結來改善電容的特性。同時也可以抑制介面層成長,得到較薄的EOT,來改善電容的特性,在漏電流、崩潰電場、崩潰電荷上皆可得到明顯的改善。
Abstract
In this thesis, we used high-k materials Gd2O3, Ta2O5 and Er2O3 to replace traditional SiO2 insulator for applying in polycrystalline thin film process. The RF sputtering was used to deposit these three high-k material layers combined with post-RTA treatment to remove and passivate the defects between the high-κ materials and the polysilicon in order to improve the characteristics of the poly-oxide capacitors.
In polycrystalline silicon study, there are existed some drawbacks such as interface roughness, interface trap states, and grain boundary trap states in polycrystalline silicon. Therefore, it’s necessary to improve polyoxide quality such as higher breakdown field, lower charge trapping, and lager charge to breakdown. In this thesis, those new high-k materials as dielectric capacitors were deposited in polycrystalline silicon, which have higher dielectric constant, lower charge density, higher breakdown electric field and better thermal stability, and combined with RTA treatment to investigate the electrical and physical characteristics.
According to the results, it can be seen that by RTA treatment, those defects and trap states existed in the high-k and polysilicon grain boundary were passivated to form stronger bondings by the post rapid thermal annealing treatment for the improvement of electrical characteristics of the high-k capacitors. Furthermore, the high-k deposition with RTA treatment, the growth of interfacial layer can be suppressed to get thinner effective oxide thickness (EOT); and improve the electrical characteristics such as lower leakage currents, higher breakdown electric fields and larger charg-to-breakdowns.
Contents
Acknowledgment i
Chinese Abstract iii
English Abstract iv
Contents v
Figures Captions and Tables viii
Chapter 1 Introduction……………………………….……………………….1
1.1 Background………………………………………………………1
1.2 The limit of gate oxide scale……………………………………..2
1.3 Overview of Low Temperature poly-si Thin-Film
Transistors…………...…………………………………………...3
1.4 High-k Gate Dielectric…………………………………………...4
1.4.1 Issues of High K Material………………………………….5
1.4.2 Preparation of High K material…………………………….6
1.5 The motivation in this study……………………………………..7
1.6 Thesis Organization………………………...……………………7
Reference…………………………….………………………………9

Chapter 2 Electrical and Physical Characteristics of Gd2O3 Polyoxide Capacitors……………………………………………………12
2.1 Introduction………………………………………………..……12
2.2 Experiment……….………….………………………………….13
2.3 Physical Characterization.…………………..…………………..14
2.3.1X-ray diffraction (XRD) of Gd2O3 film
analysis……..……………………………………………...14
2.3.2X-ray photoelectron spectroscopy (XPS)…………............15
2.3.3Atomic force microscope (AFM) of Gd2O3 film
analysis…………..……………………………………….. 17
2.4 Electrical Characterization……………………………………...17
2.5Summary……………….………………………….…….19
Reference…………………………………………………………...20

Chapter 3 Electrical and Physical Characteristics of Ta2O5 Polyoxide
Capacitors…………………………………..…………………….34
3.1 Introduction………………………………………………..……34
3.2 Experiment………………….………………………………….35
3.3 Physical Characterization…………………..…………………..36
3.3.1X-ray diffraction (XRD) of Ta2O5 film
analysis………………………………………………….…36
3.3.2X-ray photoelectron spectroscopy (XPS)…………............37
3.3.3Atomic force microscope (AFM) of Ta2O5 film
analysis…………..……………………………………….. 39
2.4 Electrical Characterization……………………………………...39
2.5Summary……………….………………………….…….41
Reference…………………………………………………………...42

Chapter 4 Electrical and Physical Characteristics of Er2O3 Polyoxide
Capacitors…………………………………..…………………….57
4.1 Introduction………………………………………………..……57
4.2 Experiment………………….………………………………….58
4.3 Physical Characterization…………………..…………………..59
4.3.1X-ray diffraction (XRD) of Er2O3 film
analysis………………………………………………….…59
4.3.2X-ray photoelectron spectroscopy (XPS)…………............60
4.3.3Atomic force microscope (AFM) of Er2O3 film
analysis…………..……………………………………….. 62
4.4 Electrical Characterization……………………………………...63
4.5Summary……………….………………………….…….65
Reference…………………………………………………………...66

Chapter 5 Conclusions and Future Works...............................................80
5.1 Conclusion…..…………….…………………….……………...80
5.2 Future works………………...……….………………….........81
Reference…………………………………………………………...82
Publications List……………………………………………
Figures Captions and Tables
Chapter 1
Fig. 1.1 Conduction mechanism in oxide for the MOS structure.
Fig. 1.2 Issues for choosing a high-k material.
Table. 1-1 This sheet is a demonstration about the comparisions of physical
characteristics of High-k
Chapter 2
Fig. 2-1 Schematic polyoxide capacitors cross-section detailed process
flow
Fig. 2-2 XRD of Gd2O3 film after annealing at various temperature in
N2 ambient for 30 sec.
Fig. 2-3 XPS results of (a) Gd 4d, (b) Si 2p, (C)O1s Gd2O3 film after
annealing at various temperature in N2 ambient for 30 sec.
Fig. 2-4 AFM image of Gd2O3 surface of control sample with
roughness root mean square (rms) of 5.432 nm.
Fig. 2-5 AFM image of Gd2O3 surface of RTA7000C sample with
roughness root mean square (rms) of 4.576 nm.
Fig. 2-6 AFM image of Gd2O3 surface of RTA9000C sample with
roughness root mean square (rms) of 3.788 nm.
Fig. 2-7 AFM image of n+-polysilicon surface of control sample with
roughness root mean square (rms) of 5.91 nm.
Fig. 2-8 AFM image of n+-polysilicon surface of RTA9000C sample
with roughness root mean square (rms) of 4.973 nm.
Fig. 2-9 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for control sample with a CET 146Å.
Fig. 2-10 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA7000C sample with a CET 122Å.
Fig. 2-11 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA8000C sample with a CET 111Å.
Fig. 2-12 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA9000C sample with a CET 102Å.
Fig.2-13 The J-E characteristics of the control, RTA7000C, RTA8000C
and RTA9000C on gate dielectric/n+-polysilicon films for the
top gate applied with a negative bias.
Fig.2-14 The J-E characteristics of the control, RTA7000C, RTA8000C
and RTA9000C on gate dielectric/n+-polysilicon films for the
top gate applied with a positive bias.
Fig. 2-15 The curves of gate voltage shifts (△Vg) versus stress time of
the control, RTA7000C, RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for the top gate applied with a negative gate constant current (under -0.5μA/cm2) stress.
Fig. 2-16 The curves of gate voltage shifts (△Vg) versus stress time of
the control, RTA7000C, RTA8000C and RTA9000C on gate
dielectric/n+-polysilicon films for the top gate applied with a
positive gate constant current (under 0.05μA/cm2) stress.
Fig.2-17 The Weibull distribution Qbd plots for the control, RTA7000C,
RTA8000C and RTA9000C on gate dielectric/n+-polysilicon
films for the top gate applied with a negative bias.

Fig.2-18 The Weibull distribution Qbd plots for the control, RTA7000C,
RTA8000C and RTA9000C on gate dielectric/n+-polysilicon
films for the top gate applied with a positive bias.
Chapter 3
Fig. 3-1 Schematic polyoxide capacitors cross-section detailed process
flow
Fig. 3-2 XRD of Ta2O5 film after annealing at various temperature in
N2 ambient for 30 sec.
Fig. 3-3 XPS results of (a) Ta 4d, (b) Si 2p, (C)O1s Ta2O5 film after
annealing at various temperature in N2 ambient for 30 sec.
Fig. 3-4 AFM image of Ta2O5 surface of control sample with
roughness root mean square (rms) of 6.19 nm.
Fig. 3-5 AFM image of Ta2O5 surface of RTA6000C sample with
roughness root mean square (rms) of 5.232 nm.
Fig. 3-6 AFM image of Ta2O5 surface of RTA8000C sample with
roughness root mean square (rms) of 3.298 nm.
Fig. 3-7 AFM image of Ta2O5 surface of RTA9000C sample with
roughness root mean square (rms) of 5.578 nm.
Fig. 3-8 AFM image of n+-polysilicon surface of control sample with
roughness root mean square (rms) of 5.472 nm.
Fig. 3-9 AFM image of n+-polysilicon surface of RTA8000C sample
with roughness root mean square (rms) of 3.590 nm.
Fig. 3-10 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for control sample with a CET 97.1Å.
Fig. 3-11 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA6000C sample with a CET 88.7Å.
Fig. 3-12 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA7000C sample with a CET 80.7Å.
Fig. 3-13 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA8000C sample with a CET 73.7Å.
Fig. 3-14 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA9000C sample with a CET 81.7Å.
Fig.3-15 The J-V characteristics of the control, RTA6000C, RTA7000C ,
RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for
the top gate applied with a negative bias.
Fig.3-16 The J-V characteristics of the control, RTA6000C, RTA7000C,
RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for
the top gate applied with a positive bias.
Fig. 3-17 The curves of gate voltage shifts (△Vg) versus stress time of
the control, RTA6000C, RTA7000C, RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for the top gate applied with a negative gate constant current (under -50μA/cm2) stress.
Fig. 3-18 The curves of gate voltage shifts (△Vg) versus stress time of
the control, RTA6000C, RTA7000C, RTA8000C and RTA9000C on
gate dielectric/n+-polysilicon films for the top gate applied with a
positive gate constant current (under 5μA/cm2) stress.
Fig.3-19 The Weibull distribution Qbd plots for the control, RTA6000C,
RTA7000C,RTA8000C and RTA9000C on gate
dielectric/n+-polysilicon films for the top gate applied with a
negative bias.
Fig.3-20 The Weibull distribution Qbd plots for the control, RTA7000C,
RTA7000C,RTA8000C and RTA9000C on gate
dielectric/n+-polysilicon films for the top gate applied with a positive
bias.
Chapter 4
Fig. 4-1 Schematic polyoxide capacitors cross-section detailed process
flow
Fig. 4-2 XRD of Er2O3 film after annealing at various temperature in
N2 ambient for 30 sec.
Fig. 4-3 XPS results of (a) O1s, (b) Er 4d Er2O3 film after
annealing at various temperature in N2 ambient for 30 sec.
Fig. 4-4 AFM image of Er2O3 surface of control sample with
roughness root mean square (rms) of 7.381 nm.
Fig. 4-5 AFM image of Er2O3 surface of RTA6000C sample with
roughness root mean square (rms) of 6.910 nm.
Fig. 4-6 AFM image of Er2O5 surface of RTA8000C sample with
roughness root mean square (rms) of 5.626 nm.
Fig. 4-7 AFM image of Er2O5 surface of RTA9000C sample with
roughness root mean square (rms) of 6.489 nm.
Fig. 4-8 AFM image of n+-polysilicon surface of control sample with
roughness root mean square (rms) of 7.896 nm.
Fig. 4-9 AFM image of n+-polysilicon surface of RTA8000C sample
with roughness root mean square (rms) of 5.846 nm.
Fig. 4-10 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for control sample with a CET 182Å.
Fig. 4-11 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA6000C sample with a CET 175Å.
Fig. 4-12 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA7000C sample with a CET 160Å.
Fig. 4-13 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA8000C sample with a CET 153Å.
Fig. 4-14 The high frequency C-V characteristics of aluminum/polyoxide/
n+-polysilicon for RTA9000C sample with a CET 166Å.
Fig.4-15 The J-V characteristics of the control, RTA6000C, RTA7000C ,
RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for
the top gate applied with a negative bias.
Fig.4-16 The J-V characteristics of the control, RTA6000C, RTA7000C,
RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for
the top gate applied with a positive bias.
Fig. 4-17 The curves of gate voltage shifts (△Vg) versus stress time of
the control, RTA6000C, RTA7000C, RTA8000C and RTA9000C on gate dielectric/n+-polysilicon films for the top gate applied with a negative gate constant current (under -0.05μA/cm2) stress.
Fig. 4-18 The curves of gate voltage shifts (△Vg) versus stress time of
the control, RTA6000C, RTA7000C, RTA8000C and RTA9000C on
gate dielectric/n+-polysilicon films for the top gate applied with a
positive gate constant current (under 0.05μA/cm2) stress.
Fig.4-19 The Weibull distribution Qbd plots for the control, RTA6000C,
RTA7000C,RTA8000C and RTA9000C on gate
dielectric/n+-polysilicon films for the top gate applied with a
negative bias.
Fig.4-20 The Weibull distribution Qbd plots for the control, RTA6000C,
RTA7000C,RTA8000C and RTA9000C on gate
dielectric/n+-polysilicon films for the top gate applied with a positive
bias.
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