臺灣博碩士論文加值系統

近年來，懸浮閘極記憶體已經被廣泛低使用在非揮發性的資料儲存上。然而，對於利用複晶矽當作儲存電荷層的傳統式懸浮閘極記憶體元件來說，有幾項主要的缺點是極需被克服的，例如:元件尺寸微縮所面臨的瓶頸、較高的操作電壓、較差的資料保存時間。為了解決上文所述的這些問題，一種擁有分離式儲存電荷節點的奈米點記憶體已經被發表出來，並且極有可能去取代掉原本的懸浮閘極記憶體。
在此篇論文當中，我們研究了利用基板的高低接面以及氨的電漿處理在已經被發表的氧化釓奈米點記憶體上。利用硼的參雜產生基板的高低接面可以有效的增加氧化釓奈米點記憶體的記憶窗及寫入電子的效率，並且可以達到很好的電子寫入/抹除容忍度。利用氨的電漿處理在氧化釓奈米點記憶體上可以達到很大的記憶窗，並且可以改善電子的儲存持久度。這篇論文所做的研究在未來的記憶體應用上是個很好的參考研究。

Recently, floating gate memory devices widely be used in non-volatile data storage application. However, there are some major issues including devices scaling limitation, higher operation voltage and poor data retention time needed to overcome for conventional floating gate memory which employed poly-silicon as the charge storage layer. In order to solve these above issues, the nanocrystal memory devices which with discrete charge storage nodes have been proposed to be a possible candidate for the replacement of floating gate memory.
In this thesis, we propose a Gadolinium oxide (Gd2O3) nanocrystal (NC) memory structure with substrate high low junction and NH3 plasma treatment for nonvolatile flash memory application. The Gd2O3 nanocrystal memory with substrate high low junction by boron implant can improve the memory window and the program efficiency due to the hot carrier injection, and also get the good data endurance. The NH3 plasma treatment for Gd2O3-NC memory can improve the memory window and the data retention. This study can be the candidate for the next generation for the memory application.

Table of Contents
Acknowledgement……………………………………………………….i
Chinese abstract…………………………………………...……………ii
English abstract………………………………………………………...iii
Content..………………...………………………………………………iv
Content of figure.……………………………………………………….vi

Content
Chapter 1 Introduction
1-1 Background ………..…...……………………………………………1
1-2 Nanocrystal memory….…………………………...…………………2
1-3 Gd2O3 metal-oxide NC memory...………………..….…………….. 3
1-4 The motivation of this study . ………………………….……........... 4
1-5 Thesis organization…………………………………………………..4

Chapter 2 Improved Characteristic of Gd2O3 Nanocrystal Memory with Substrate High-Low Junction by Using Backside p+ Doped Induced Hot Carrier Injection.
2-1 Introduction ………………………………………..……………….11
2-2 Experiment ……………...………………………………………….11
2-3 Results and Discussion...…………………….………..…………….12
2-4 Summary ……………………………………….….……….............15



Chapter 3 The Characterization of Gd2O3-NC memory by post NH3 plasma treatment.
3-1 Introduction ………………………………………..……………….30
3-2 Experiment ……………...………………………………………….30
3-3 Results and Discussion...…………………….………..…………….31
3-4 Summary ……………………………………….….……….............33

Chapter 4 Conclusions and future works
4-1 Conclusions of this study……………….…………….…………….50
4-2 Future works ………………………………….…………….………50

Reference ……………………………………………..………….…….52

Content of Figure
Fig. 1-1 The schematic cross section of floating gate memory structure.
Fig. 1-2 The schematic band diagram of Al2O3 tunneling barrier using on memory.
Fig. 1-3 The schematic cross section of SONOS memory structure. Fig. 1-4 (a) The schematic cross section of the nanocrystal memory
structure.(b) The TEM image of Ge nanocrystal.
Fig.1-5 Fig. 1-5 The band diagrams of metal nanocrystal memory structure.
Fig.1-6 The band diagrams of Gd2O3 nanocrystal memory structure.
Fig. 1-7 The TEM image of Gd2O3 nanocrystal memory structure.
Fig. 2-1 The process flow of Gd2O3 nanocrystal memory with substrate high-low junction experiment.
Fig. 2-2 SIMS analysis of the wafers with backside boron implant and annealed by RTA (PR) and furnace (PF).
Fig. 2-3 The TEM image of Gd2O3 nanocrystal memory.
Fig. 2-4 C-V Hysteresis of N sample which is swept from -17V to 17V and then swept back.
Fig. 2-5 C-V Hysteresis of P sample which is swept from -17V to 17V and then swept back.
Fig. 2-6 C-V Hysteresis of PR sample which is swept from -17V to 17V and then swept back.
Fig. 2-7 C-V Hysteresis of PF sample which is swept from -17V to 17V and then swept back.
Fig. 2-8 Normalized C-V hysteresis curves of the Gd2O3-NC memory. The inset shows the large memory window for the PR sample.
Fig. 2-9 Program speed of the Gd2O3-NC memory for Vg＝16, 17, and 18 V. The inset shows the higher program speed of the PR sample..
Fig. 2-10 Schematic of band diagrams at the programmed state for n-type.
Fig. 2-11 Schematic of band diagrams at the programmed state for p-type.
Fig. 2-12 Schematic of band diagrams at the programmed state for PR-type. The BTBT hot carrier is injected due to the high-low junction of the PR sample.
Fig. 2-13 Erase speed of the Gd2O3-NC memory for Vg＝-16, -17, and -18 V. The inset shows that the erase speed of all the samples are almost the same.
Fig. 2-14 The constant electrical field of retention mode for Vg=Vfb.
Fig. 2-15 The retention characteristics of the Gd2O3-NC memory under constant electric field stress. The inset shows the TEM image of our Gd2O3 NC memory.
Fig. 2-16 Schematic of band diagrams for the retention under constant electric field stress, where the gate bias is (a) positive and (b) negative.
Fig. 2-17 Arrhenius plot of charge loss characteristic with 298K to 358K for the Gd2O3-NC memory. The activation energies of all samples are almost the same
Fig. 2-18 P/E cycling of the N and PR samples. The program pulse is 17 V for 10 ms and erase is -17 V for 500 ms.
Fig. 3-1 The process flow of Gd2O3 nanocrystal memory with NH3 plasma treatment experiment.
Fig. 3-2 The C-V hysteresis curve of the control sample. The gate voltage was swept from -16V to +16V and then swept back.
Fig. 3-3 The C-V hysteresis curve of the P5600 sample. The gate voltage was swept from -16V to +16V and then swept back.
Fig. 3-4 The C-V hysteresis curve of the P5700 sample. The gate voltage was swept from -16V to +16V and then swept back.
Fig. 3-5 The C-V hysteresis curve of the P5800 sample. The gate voltage was swept from -16V to +16V and then swept back.
Fig. 3-6 The extracted memory windows of these samples. A larger memory window can be obtained for P5600 and P5700 samples.
Fig. 3-7 Program speed of Gd2O3-NC memory. The gate voltage is 14V and the pulse width varies from 1e-4s to 1s.
Fig. 3-8 Program speed of Gd2O3-NC memory. The gate voltage is 15V and the pulse width varies from 1e-4s to 1s.
Fig. 3-9 Program speed of Gd2O3-NC memory. The gate voltage is 16V and the pulse width varies from 1e-4s to 1s.
Fig. 3-10 The extracted memory windows for program pulse at 1s of these samples. A larger memory window can be obtained for P5600 and P5700 samples.
Fig. 3-11 The erase speed of the Gd2O3-NC memory. The gate voltage is -14V the pulse width varies from 1e-3s to 10s.
Fig. 3-12 The erase speed of the Gd2O3-NC memory. The gate voltage is -15V the pulse width varies from 1e-3s to 10s.
Fig. 3-13 The erase speed of the Gd2O3-NC memory. The gate voltage is -16V the pulse width varies from 1e-3s to 10s.
Fig. 3-14 The retention characteristic of 25℃. Curve 1 is the data fitting from 0s to 3000s, curve 2 is from 4000s to 10000s.
Fig. 3-15 The retention characteristic of 55℃. Curve 1 is the data fitting from 0s to 3000s, curve 2 is from 4000s to 10000s.
Fig. 3-16 The retention characteristic of 55℃. Curve 1 is the data fitting from 0s to 3000s, curve 2 is from 4000s to 10000s.
Fig. 3-18 Schematic band diagram of control sample.
Fig. 3-19 Schematic band diagram of P5600 sample.
Fig. 3-20 Schematic band diagram of P5800 sample. The trap state can be decreased for the P5800 sample, indicating the good retention.
Fig. 3-21 Arrhenius plot of charge loss characteristic with 298K to 358K for the Gd2O3-NC memory. The activation energy of P5800 sample is larger than others.
Fig. 3-22 The endurance characteristic of control and P5600 samples.
List of Tables
Table 1 The detail process of Gd2O3 nanocrystal memory with substrate high-low junction experiment.………………..15
Table 2 The detail process of Gd2O3 nanocrystal memory with NH3 plasma treatment experiment……………………………35
Table 3 High-low junction……………………………………….51
Table 4 NH3 plasma……………………………………………...51

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