臺灣博碩士論文加值系統

本論文中採用標準 CMOS模型，來實現一個低功率消耗的10~30 GHz超寬頻收發器。發射器以一個數位的脈波產生器與脈波調變器，產生一個狹窄的脈衝信號並且經由Chebyshev帶通濾波器濾掉不需要的波段。發射信號所採用的編碼方式為PCM，在頻域上符合IEEE 802.16之傳輸規範。接收器使用分布式放大器將接收到超寬頻的信號放大，經由平方器與積分器降頻，比較器判斷得到的方波信號。將此方波信號送入NRZ編碼器做修正，再與PRBS編碼信號進行解調的動作，解讀出由發射器傳送過來的資料信號。
在本論文中，電路採用安捷倫公司的ADS軟體模擬。發射器模擬方面，輸出脈衝寬度0.03ns，振幅135mV，其頻譜於10~30 GHz皆有約-45dBm之功率。發射器消秏功率為18mW，晶片面積為0.832 × 0.943 mm2。接收器模擬方面，分佈式放大器於10~30GHz 之增益相當平坦且大小為8dB，雜訊指數亦皆小於7dB。類比積分器所採用的轉導放大器(OTA)的轉導值在200MHz時有5mS。接收器的晶片面積為1.394 × 1.195 mm2，功率消耗為82mW。量測方面，發射器以TSMC CMOS 0.13μm製程完成晶片製作。消耗功率為18mW符合低功率之設計規格。頻率為13GHz時，其頻譜強度最大值為-42dBm。脈衝振幅最大值為180mV，其相對脈衝寬度為11ns。

This thesis presents the development of low-power 10~30 GHz UWB transmitter and receiver circuits with standard CMOS technology. In the transmitter, a digital pulse generator with PCM modulator is presented. The modulated pulse is further shaped by a Chebyshev band pass filter and meets the spectral mask specification of IEEE 802.16 . In the receiver, the received signal is amplified by distributed amplifier. The amplified signal is sent to the squarer circuit and then into an OTA-C integrator. The comparator changes the analog signal which comes from the integrator output to digital signal. Because the digital signal is not close to the correct square waveform, the NRZ encoder is used to fix up the digital signal and receiver recovers the transmitted data with PRBS code.
The circuits are simulated by Agilent ADS software. Results of transmitter simulations show the width of impulse is 0.03ns, and the peak to peak of impulse waveform is 135mV. The power spectrum is approximately -45-dBm in 10~30-GHz. The power consumption of transmitter is 18mW and the die size of 0.832 × 0.943 mm2. The simulation results of receiver show the gain of the proposed distributed amplifier of flatness within 10~30 GHz to be 8dB. The Noise figure is approximately smaller than 7dB and the gm of the OTA-C integrator is 5mS. The power consumption of receiver is 82mW and the die size of 1.394 × 1.195 mm2. Based on the measurement results of the transmitter, power consumption is good agreement to the simulation of 18mW. The maximal value of power spectrum is -42-dBm. The width of impulse is 11ns, and the peak to peak voltage of output waveform is 180mV.

目 錄
指導教授推薦書
口試委員審定書
圖書館授權書………………………………………………………….iii
誌謝……………………………………………………………………..iv
中文摘要…………………………………………………………………v
英文摘要………………………………………………………………vi
目錄……………………………………………………………………..vii
圖目錄…………………………………………………………………xi
表目錄…………………………………………………………………xvi
第一章 緒論
1.1簡介……………………………………………………………....1
1.2研究動機…………………………………………………………4
1.3論文架構…………………………………………………………5
第二章 超寬頻系統分析
2.1超寬頻技術的發展歷程……………………….………………...6
2.2超寬頻的技術歸納………………………………………………7
2.2.1脈衝無線電……………………………………………8
2.2.2直接序列展頻 (DS-UWB)……………………………9
2.2.3正交分類多工 (MB-OFDM)…………………….……11
2.3超寬頻通訊系統架構……………………………………….….13
2.4脈衝信號調變…………………………………………….…….14
2.5資料信號編碼…………………………………………………..17
第三章 脈衝式超寬頻發射器之分析與設計
3.1脈衝式超寬頻簡介…………………………………….……….18
3.2脈衝式超寬頻發射器的技術特點………………….………….19
3.3傅立葉分析(Fourier Analysis)……………………………….…22
3.3.1傅立葉轉換(Fourier Transform)…………………..……...22
3.3.1.1連續時間的傅立葉轉換(CTFT)…………………24
3.3.1.2 離散時間的傅立葉轉換(DTFT)………………..24
3.3.1.3 傅立葉轉換存在的充分條件…………………...25
3.3.2傅立葉級數(Fourier Series)………………………………25
3.3.3傅立葉轉換對功率頻譜之分析………………………….26
3.3.2.1 能量與功率之時域分析………………………...26
3.3.2.2 能量與功率之頻域分析………………………...26
3.3.2.3 週期訊號的功率密度頻譜……………………...27
3.3.2.4 連續弦波信號與脈波信號之功率頻譜比較…...28
3.4脈衝式超寬頻發射器架構分析.…………………………...…..29
3.4.1前言………………………………………………….……29
3.4.2脈衝式超寬頻發射器電方塊圖說明……………….……30
3.4.3脈衝式超寬頻發射器電路分析………………………….32
3.4.3.1脈波產生器電路分析……………………………32
3.4.3.2擬隨機二位原序列產生器電路設計……………33
3.4.3.3脈波調變氣電路設計……………………………36
3.4.3.4濾波器的特性分析與電路設計…………………37
3.4.3.4.1低通濾波器至帶通濾波器的轉換…….40
3.4.3.4.2 Chebyshev 帶通濾波器設計……….…42
3.5脈衝式超寬頻發射器模擬結果(Post-sim)與電路佈局圖..…....44
3.6脈衝式超寬頻發射器預計規格列表…………………………..50
第四章 脈衝式超寬頻接收器之分析與設計
4.1脈衝式超寬頻收發器簡介……………………………………..51
4.2脈衝式超寬頻接收器架構分析………………………………..52
4.2.1前言………………………………………………………52
4.2.2脈衝式超寬頻接收器方塊圖說明………………………53
4.2.3脈衝式超寬頻接收器電路設計…………………………54
4.2.3.1分布式放大器………………………………….………54
4.2.3.2平方器電路設計…………………………………….…57
4.2.3.2.1前言………………………………………….57
4.2.3.2.2平方器電路設計與分析…………………….58
4.2.3.3積分器電路設計……………………………….………60
4.2.3.3.1運算轉導放大器……..…………………...…60
4.2.3.3.2 運算轉導放大器之應用……………..…….62
4.2.3.3.3 OTA-ground capacitor完整電路圖………...64
4.2.3.4比較器(Comparator)電路設計………………..……….65
4.2.3.5 NRZ(Non-Return to Zero)編碼電路設計…………..…67
4.2.3.5.1 前言………………………………………...67
4.2.3.5.2 NRZ編碼概念與電路設計…………..…..68
4.2.3.6 脈波解調電路設計……………………………………70
4.3 脈衝式超寬頻接收器模擬(Post-sim)與電路佈局…….……71
4.4脈衝式超寬頻接收器預計規格表…………………..…………78
第五章 晶片量測與討論
5.1脈衝式超寬頻發射器量測……………………………………..79
5.1.1前言………………………………………………...……..79
5.1.2佈局晶片照片…………………………………………….80
5.1.3量測環境………………………………………………….81
5.1.4量測結果………………………………………………….82
5.1.5量測結果討論…………………………………………….87
5.2脈衝式超寬頻收發器與相關文獻之比較……………………..87
第六章結論與未來展望………………………………………………...92
6.1結論……………………………………………………………..92
6.2 未來展望……………………………………………………….93
參考文獻………………………………………………………………...94



圖 目 錄
圖1.1 FCC所定義之UWB說明圖………………………………...…….2
圖1.2 UWB 與傳統的窄頻訊號比較之示意圖………………………...2
圖1.3 UWB/802.16之頻譜規範………….…………………….………..3
圖2.1直接展頻(DSSS)之例子………………………………….…….....9
圖2.2 DS-CDMA發射器方圖………………………………………….10
圖2.3 Multi-band OFDM 調變訊號頻譜分配圖………………………11
圖2.4以時間交錯方式利用多個次頻帶傳送OFDM符碼…………...12
圖2.5傳統超寬頻收發器架構…………………………………………13
圖2.6 10-30 GHz脈衝式超寬頻收發器架構圖………………………..13
圖2.7脈波位置調變(Pulse Position Modulation，PPM)……………...14
圖2.8脈波振幅調變(Pulse Amplitude Modulation，PAM)…………...15
圖2.9相位調變(Bi-Phase Modulation)…………………………………15
圖2.10開關鍵(On-Off Keying，OOK)…………………………………16
圖2.11 發射器資料信號編碼波形圖………………………………….17
圖3.2 為圖3.1訊號的傅立葉轉換之振幅頻譜………………………23
圖3.3 連續弦波波形圖與功率頻譜圖………………………………...28
圖3.4 單一脈波之波形圖與功率頻譜圖……………………………...28
圖3.5 脈衝式超寬頻發射器電路方塊圖……………………..…….…30
圖3.6 Pulse Generator電路方塊圖……………………………………..32
圖3.7 Voltage Control Delay Circuit電路圖……………………………33
圖3.8 TSPC-DFF除二之除頻器電路圖……………………………..33
圖3.9 PRBS Generator電路圖………………………………………..34
圖3.10 單一級Shift Register電路圖………………………………….34
圖3.11 LFSR各節點電壓模擬波形圖…………………………………35
圖3.12 Pulse Modulator邏輯電路圖…………………………………36
圖3.13 濾波器的分類(a)低通濾波器(b)高通濾波器(c)帶通濾波器
(d)帶斥濾波器………………………………..…………...….38
圖3.14 濾波器的轉換原理…………………………………………...40
圖3.15 低通濾波器轉換成帶通濾波器各元件的轉換……………….40
圖3.16 Chebyshev帶通濾波器電路……………………………………41
圖3.17 發射器各節點波形模擬結果…………………………………..44
圖3.18 發射器輸出波形放大圖……………………………………….45
圖3.19 Vdct=0.4V時之延遲電路輸入與輸出電壓波形圖…………...45
圖3.20 Vdct=0.42V時之延遲電路輸入與輸出電壓波形圖………….45
圖3.21 Vdct=0.44V時之延遲電路輸入與輸出電壓波形圖………….46
圖3.22 Vdct=0.48V時之延遲電路輸入與輸出電壓波形圖………….46
圖 3.23 Vdct=0.5V時之延遲電路輸入與輸出電壓波形圖………..….46
圖 3.24 Vdct偏壓與延遲時間關係圖………………………………..47
圖 3.25 Chebyshev BPF s-parameter 模擬圖(Post-Sim)…………....48
圖 3.26 超寬頻發射器輸出頻譜(Post-Sim)...….……………..………48
圖 3.27 脈衝式超寬頻發射器電路佈局平面圖……………………....49
圖 4.1 脈衝式超寬頻收發器方塊圖…………………………………51
圖 4.2 脈衝式超寬頻接收器電路方塊圖……………………………53
圖 4.3 3.1~30GHz分佈式放大………………………………….....…54
圖 4.4 3.1~30GHz分布式放大器Gain(S21)量測圖…………….…..55
圖 4.5 3.1~30GHz分布式放大器Noise Figure量測圖…………..…56
圖 4.6 micro-mixer電路圖………………………………………...…58
圖 4.7 Squarer電路圖……………………………………………...…58
圖 4.8 OTA 的電路符號………………………..………………...…60
圖 4.9 OTA 的理想等效模型……..…………………………………..61
圖 4.10 OTA 的真實等效模型…………………………..……………61
圖 4.11 OTA 電路圖……….………………………………………….61
圖 4.12 OTA電壓放大器…………………………………………….63
圖 4.13 OTA電流放大器…………………………………………….63
圖 4.14OTA電流積分器…………………...…………………………..63
圖 4.15 OTA電壓積分器………………………………………………64
圖 4.16 CMOS OTA-C 積分器電路圖………………………………..64
圖 4.17 比較器電路基本架構圖……………………………………...65
圖 4.18 (a)比較器之零階轉換曲線 (b)比較器之一階轉換曲線….....65
圖 4.19 CMOS比較器電路圖…………………………………………66
圖 4.20 平方器、積分器與比較器輸出電壓模擬圖……………….67
圖4.21 NRZ編碼使用時脈產生器電路圖……………………….…68
圖4.22、解調器電路…………………………………………………..70
圖4.23 平方器輸入電壓波形圖……………………………………..71
圖 4.24 平方器輸出電壓波形圖……………………………………..71
圖 4.25 電壓控制可調延遲電路之延遲時間與控制電壓關係圖…71
圖 4.26、發射器各節點電壓波形模擬圖(Postsim)……………………72
圖 4.27 接收器各節點電壓波形模擬圖(Post-sim)……...………......73
圖 4.28 Vdata=10101010時接收器各節點之模擬電壓波形圖..……74
圖 4.29 Vdata=01011001時接收器各節點之模擬電壓波形圖..……75
圖 4.30 脈衝式超寬頻接收器佈局平面圖……………..…………...77
圖 5.1超寬頻發射電路之佈局晶片圖……………………………...…80
圖 5.2實際量測的照片…………………………………………….…..80
圖 5.3晶片量測使用之儀器照像圖…………………………………...82
圖 5.4 輸出頻譜量測圖(1)….………………………………………..82
圖 5.5輸出頻譜量測圖(2)……………………………......………..83
圖 5.6 Vclk=400MHz,Vdata=50MHz時之輸出頻譜量測圖(1)…..84
圖 5.7 輸出波形量測圖(2)………………………………………….85
圖5.8 輸出波形量測圖(3)……………………………………………86
圖5.9 輸出波形放大圖………………………….……………………86









表 目 錄
表3.1、LFSR Sequence節點變化表格…………………………….….35
表3.2 Chebyshev 低通濾波器正規化係數表(0.5dB漣波) (N=1 to 10)...........………………………………………………………………..42
表3.3電壓變動比較表(Postsim)……………………………….……48
表3.4溫度變動比較表(Postsim)………….…….................…………..48
表3.5 製程變異比較表(Postsim)……………………………………..48
表 3.6 10~30 GHz脈衝式超寬頻發射器預計規格列表…………..50
表 4.1 3.1~30 GHz 分布式放大器量測結果之規格………...……...56
表 4.2 電壓變動比較表(Postsim)…………………………………......76
表 4.3 溫度變動比較表(Postsim)………………………………….….76
表4.4、製程變異比較表(Postsim)……………………………………76
表 4.5超寬頻接收器規格列表(Post-sim)………………..……………78
表 5.1 ADS模擬發射器與量測結果比較………………….…...……..86
表 5.2 Transmitter 比較表……………….………………………...…..90
表 5.3 Receiver 比較表………………………………………………..91

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