臺灣博碩士論文加值系統

中文摘要
在這份論文中，我們實現了兩大主題，一是利用選擇性液相沉積的氧化層，以簡化瓶型深溝槽式電容器之製作流程，用來增加電容器的表面積，另一個是將全新的製程”微秒快閃回火”，導入DRAM量產製程之中，以改善元件特性並觀察其應用於各個回火步驟之影響。
利用氫氟矽酸(H2SiF6)加水所長成的氧化層(S-LPD oxide)具有選擇特性，只有沉積在深溝槽上部的側壁，不會沉積在深溝槽下部的光阻上，因此，在溝槽下部的光阻上被硫酸去除後，S-LPD氧化層被留下來，當成罩幕程層，用以保護深溝槽上部的矽，接著再以氨水去除深溝槽下部的矽，以形成瓶型深溝槽，這樣的創新作法首度在 DRAM上被驗證，並成功地簡化60%以上之電容器製作流程，而且瓶型電容器的容量，經電性驗證，可以增加20%以上。
全新的製程”微秒快閃回火”，從未被應用在DRAM上量產過，我們首度透過一系列的實驗，來觀察在DRAM製程中，哪些步驟導入這個製程對DRAM的漏電現象有改善，並且不影響DRAM的基本功能，甚至增加效能。我們發現DRAM外圍電路NMOS元件的靜止漏電量減少36%，閘極衍生之汲極漏電流(GIDL)在最佳條件時，array區的NMOS及外圍電路的NMOS 與PMOS，可以分別地降低14.5%, 15%, 及39%. 另外，在附錄中特別就三維元件在未來DRAM的應用與挑戰提出探討與回顧。

Abstract
Process integration of device improvements in DRAM by selective liquid phase deposition oxide and millisecond flash anneal has been demonstrated. The processes of forming a bottle shape trench capacitor in DRAM have been simplified by over 60% using selective liquid phase deposition (S-LPD) oxide. It is the very first time been used on trench DRAM manufacturing. This S-LPD oxide is formed by hexa-fluosilic acid (H2SiF6) and water without H3BO3 on photo resist inside of deep trench (DT) sidewall. LPD oxide becomes a protective layer on DT upper portion. Then the DT bottom portion was enlarged to form a trench bottle by NH4OH. Compared to conventional DT, 20% of capacitance was enhanced by this S-LPD process.
For the reduction of DRAM gate induced drain leakage (GIDL), millisecond flash anneal (MFLA) has been demonstrated on a 140nm DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application. The periphery NMOS off-current was reduced by 36%. This off-current improvement reduced the standby current by 5% in a DRAM functional test. The GIDL reductions for an NMOS array, periphery N, and P MOS were 14.5%, 15%, and 39% respectively. A model for GIDL improvement by MFLA application was proposed. For future DRAM production, the challenges and applications of three dimensional (3-D) transistors including recessed channel transistor, fin field effect transistor (FinFET) and surrounding gate transistor (SGT) have been reviewed and listed on appendix..

Table of Contents
CHAPTER I Introduction for DRAM overview 1
1.1 Background of DRAM evolution and basic operations
1.1.1 Evolution of DRAM integrated circuits
1.1.2 Introduction of DRAM basic operations
1.2 Modern DRAM requirements and shrinkage challenges
1.2.1 Modern DRAM requirements and applications
1.2.2 The shrinkage challenges of DRAM array and periphery devices
CHAPTER II Integration of DRAM capacitor enhancement by using selective liquid-phase deposition (S-LPD) oxide 10
2.1 S-LPD oxide and it applications on trench DRAM capacitor
2.1.1 Introduction for trench DRAM capacitor and requirements
2.1.2 Benefits for S-LPD oxide and its applications
2.2 Experimental setup for S-LPD oxide on trench capacitor
2.3 Result and discussion for capacitor enhancement
2.3.1 Process simplification on deposition solutions and process steps
2.3.2 S-LPD Oxide intrinsic characteristics and step coverage
2.3.3 Surface area enhancement factors
CHAPTER III Integration of Millisecond Flash Anneal on DRAM Application 22
3.1 DRAM scaled down challenges for shallow junction devices
3.2 Basic theory of Millisecond Flash Anneal (MFLA) Process
3.3 Experimental design and process setup
3.4 DRAM device characteristics and function observation
3.4.1 Dopant diffusion, activation, poly gate grain growth, and depletion evaluation
3.4.2 Array and Periphery Device Improvement Summary
CHAPTER IV Integration of MFLA and Models 41
4.1Discussion of GIDL reduction and model setup
4.1.1 GIDL improvement and model for MFLA application
4.1.2 The observation of pre-gate oxide dopant activation by MFLA
4.1.3 The TEM observation of the NMOS junction and defects
4.1.4 Integration of RTA and MFLA for GIDL improvement
4.2 Discussion of junction breakdown improvement and model setup
4.2.1 Junction breakdown voltage improvement observation
4.2.2 Junction breakdown voltage improvement model set up
4.2.3 The Electric field for buried channel PMOSFET
CHAPTER V Conclusion 53
6.1 LPD oxide application for DRAM capacitance enhancements
6.2 MFLA application for DRAM device improvements
6.3 Future work





Appendix:
Review of three dimensional (3-D) devices for sub-60nm DRAM Application 57
A.1 Review of sub-60nm DRAM manufacturing and challenge 58
A.1.1 Technology and market environment for sub-60nm DRAM
A.1.2 Device challenges for sub-60nm DRAM
A.2 Integration of Recessed Channel Array Transistor on DRAM 60
A.2.1 Device impacts for the shape of RCAT
A.2.2 The device design benefits by using RCAT
A.2.3 Challenges and solutions for RCAT scaling
A.3 Integration of FinFET for DRAM application 76
A.3.1 Device challenges for RCAT and benefits for FinFET on DRAM
A.3.2 Outlook of FinFET fundamentals
A.3.3.1 Boundary condition of fully deplete FinFET
A.3.3.2 Threshold voltage variation of FinFET
A.3.3.3 Mobility degradation with fin thickness reduction
A.3.3.4 Gate to source drain Under-lap and over-lap
A.3.3.5 Gate Induced Drain Leakage (GIDL) for FinFET
A.3.3.6 Integration of body tied bulk FinFET on DRAM
A.4 The application and challenges of Surrounding Gate Transistor (SGT) for DRAM 94
A.4.1 Introduction of SGT DRAM application history
A.4.2 Fundamentals of SGT and its device characteristics
A.4.2.1 Benefit of SGT for DRAM
A.4.2.2 Mechanism of SGT floating body effect and its solutions
A.4.2.3 Subthreshold slope characteristics and kink effect of SGT
A.4.3 Challenges of SGT scaled down
A.4.3.1 Floating body effect
A.4.3.2 GIDL effect
A.4.4 Integration of SGT for DRAM application
A.5 Review of DRAM cell design- 8F2, 6F2 and 4F2 107
A.5.1The history of DRAM cell migration from 8F2 to 6F
A.5.2 The migration of trench to stack for DRAM production
A.5.3 Integration and devices strategy for sub-50nm 6F2 cell design
A.5.4 The migration expectation from 6F2 to 4F2 DRAM cell design
A.6 Conclusion for devices design and integration of future DRAM



List of Tables
Table 1.1 DRAM technology with band width relationships
Table 2.1 S-LPD deposition performance on deep trench
Table 3.1.the splits of MFLA demonstration in DRAM application
Table 3.2 Device performance impacts of MFLA and spike annealing at different process stages. The “–” (negative) and “+” positive numbers represent degradations and improvements, respectively, compared to that of the base line (RTA).
Table A.1 shows the electrical characteristics trend of the RCAT with several feature sizes at the same substrate doping condition.

List of Figures
Figure 1.1 the block diagram of 512M (32M x 16) DDR2.
Figure 1.2 Schematic of Basic DRAM cell
Figure 1.3 Schematic of folded bit line DRAM array
Figure 2.1 Process flow of S-LPD with trench bottle
Figure 2.2 SEM photograph of S-LPD silicon oxide against photo resist shows good step-coverage
Figure 2.3 The SEM photograph for step coverage on top of nitride and S-LPD thickness.
Figure 2.4 The SEM shows DT size enhanced 20nm per side.
Figure 2.5 shows the comparison of capacitance between base line and S-LPD with wet bottle.
Figure 3.1 Schematic drawing of the MFLA system
Figure 3.2 The 0.14μm DRAM process flow of source, drain and contact formation with MFLA applications
Figure 3.3 The schematic diagram of the device implantation position and annealing process splits.
Figure 3.4 The typical DRAM testing sequences.
Figure 3.5 Four-point-probe sheet resistance measurements of boron-implanted wafers with different MFLA temperatures.
Fig. 3.6 (a) Boron SIMS profiles for the as-implant, MFLA, and RTA splits. The boron has 2–3 nm of diffusion by MFLA. The MFLA SIMS profile has a greater linear dopant concentration in the shallow junction depth area than the RTA [68]. (b) The C-V curve for N and P MOS. Both data show no flat band voltage shift with minor interface trap found. (c) The stress comparison of product wafer before and after MFLA. It shows that the wafer stress has no degradation by MFLA on S/D annealing replacement processes.

Figure 3.7 (a) The Ion-Ioff correlation results for split MFLA R2D. NMOS Ioff is reduced by 36% or Ion is improved by 4.3%. The MFLA process temperatures (noted from A to E) vary from 1200 to 1300 ℃. (b) The MFLA R1 and MFLAR2 splits have a 5% normalized standby current reduction.
Figure 3.8 (a) shows the PMOS DIBL reduction on different process stages with MFLA temperature varying from 1200℃ to 1300℃. Process at MFLA R2 has less threshold voltage bias between linear and saturation. (b) The NMOS long channel Leff with different MFLA splits. MFLA R1 and MFLA R2 have longer channel length than that of base line.
Figure 3.9 (a) The PMOS Vt-Ion correlation of RTA replaced by MFLA. The linear fitting curve slopes for MFLA R1 and FMLA R2 are better than the base line. (b) Cell (array) Vt-Ion correlation of RTA replaced with MFLA. The slopes of the linear fitting curves for MFLA R2 and MFLA R3 are improved. (c) The NMOS Vt-Ion correlation of RTA replaced with RTA+MFLA. The linear fitting of the ion curve slope for MFLA A1 is improved. (d) The PMOS Vt roll-off with MFLA on different processes. Process at MFLA R2 has better Vt roll-off than that of MFLA R3. (e) The split MFLA R2 has better Vt roll-off than that of MFLA R3. Also in MFLA R2, 750/1260℃ split has best performance. (f) Correlation of PMOS Vt to overlap capacitance variation with MFLA R2 and R3. MFLA R2 has 100mV Vt shift and better than that of MFLA R3. It indicates that MFLA R2 has longer junction diffusion than that of MFLA R3. Both splits show 10 to 25% of improvement for overlap capacitance.
Figure 4.1 (a) 3-D chart of GIDL performance versus process stages and conditions. MFLA R3 achieves the best GIDL improvements for array NMOS, periphery N, and PMOS devices in all splits (b) Cross-section SEM image of 140-nm cell transistor with the positions identified of GIDL and junction leakage.
Figure 4.2 Plan-view TEM images of NMOS junction area defects. Images (a), (c), and (e) are bright-field data and (b), (d), and (f) are weak-beam dark-field data for RTA, spike anneal, and MFLA, respectively. Both perfect dislocation loops (PDLs) and faulted dislocation loops (FDLs) were observed.
Figure 4.3 NMOS junction TEM cross-section images of (a) RTA junction defect depth at 65.8 nm, (b) Spike anneal junction defect depth at 71.6 nm, (c) MFLA R1 junction defect depth spread from 62.9 to 72.6 nm.
Figure 4.4 HRTEM images for NMOS junction defects at {113} plane. The dislocation loops elongate along the <110> direction. The average length and width are approximately 20 and 17 nm, respectively. (c) High resolution image of faulted dislocation loop (FDL).
Figure 4.5 (a) The PMOS junction breakdown has degradation at MFLA R2 and improved at MFLA R3. (b) The NMOS junction breakdown degraded at MFLA R2 and improved at MFLA R3.
Figure 4.6 (a) shows the E-field of buried channel PMOSFET with MFLA splits. (b) The curve of E-field on different splits versus junction depth.
Figure A.1 Schematic cross section: the charge in one capacitor is accessed over two buried straps with two vertical transistor gates (one double gate transistor) and four contacts (two shared with the neighboring cells) for a low access resistance.
Figure A.2 Calculated and experimental Vt versus channel length L plot for various junction depth. Insert shows a recessed-channel NMOSFET
Figure A.3(a) Substrate doping density and maximum electric field versus DRAM technology node. (b) Comparison of the electric field between Planar TR and RCAT. (c) TEM cross section images showing excess oxidation on <110> plan and sharp top profile by furnace type thermal oxidation (left). Uniform thickness of oxide and round top profile by steam RTP type oxidation (right).
Figure A.4 Schematic illustrations of (a) planar transistor and (b) recess channel transistor. In the RCAT structure, the channel region and gate/drain overlap regions are spatially decoupled compared to that of planar structure.
Figure A.5 shows the cross-sectional electric field intensity of RCAT. The GIDL field is higher than the junction field.
Figure A.6 (a) Emax and Vth are extracted with the conditions of implantation. (b) Emax and Vth are extracted with the variations of geometry factors.
Figure A.7 (a) Junction leakage current reduce by 1order using the RCAT. (b) Distribution of contact resistance compared with RCAT and Planar transistor.
Figure A.8 (a) Correlation of Ion and Vth compared with RCAT and planar transistor. (b) Distribution of BVDS compared with RCATs and Planar transistors.
Figure A.9 Great improvement of retention time for the RCAT in 512Mb DRAM.
Figure A.10 (a) Surface potential profiles along the RCAT’s channel with various feature sizes. 10 (b) shows the trend of the DIBL versus the RCAT depths.
Figure A.11 (a) The Qbd data of array gate oxide quality is guaranteed using steam RTP type oxidation. (b) RCAT has 58% and 8% of parasitic capacitance increased for WL and BL respectively.
Figure A.12 (a) Comparison of data retention time between GWL scheme and NWL scheme with various operation voltages. Data retention time becomes worse in the NWL than in the GWL over 1.0V operation. (b) Comparison of E-FLD between WL schemes with operation voltage [12a, 12b]. 12c is the E-FLD towards the gate oxide direction and 12d is the E-FLD toward the junction direction.
Figure A.13 (a) Comparison of GIDL with Pre S/D implantations. (b) Comparison of the normalized GIDL with respect to the interaction btw landing PAD doping and post heat treatment. (c) Comparison of the normalized GIDL with respect to the interaction between landing PAD doping and post heat treatment.
Figure A.14 Schematic drawing of localized asymmetric channel device
Figure A.15 Comparison of the data retention time versus cumulative bit failure.
Figure A.16 Simulated NMOS junction profile of (a) without ESD SEG and (b) with ESD SEG.
Figure A.17 Threshold voltage roll-off characteristics with respect to the gate length and gate to DC distance.
Figure A.18 (a) Extended U-shape device (EUD) structure (recessed channel type device). The cross section in length direction is shown on the left hand side and the cross section in width direction is shown on the right hand side. (b) Ids vs. Vgate characteristics of a U-shape device with and without gate wrap-around extension: 3d simulation and experimental data.
Figure A.19 (a) shows the schematic diagram of S-Fin. The groove like RCAT with fin structure in channel width direction is formed. The operation current Iop versus Vt between RCAT and S-Fin.
Figure A.20 (a) Schematic 3-D view of novel WOB cell. (b) Cross section of the WOB cell integrated in a fully functional 512Mb DRAM: left: word line direction, right: bit line direction
Figure A.21 (a) Measured Bit line to Bit line capacitance: WOB vs. EUD vs. Planar for different ground rules. (b) Retention characteristic: WOB versus a planar 75nm technology
Figure A.22 (a) shows the layout of the 6F2 buried word line (bWL) cell. (b) The 3D simulation of the 6F2 buried word line (bWL) cell. (c) The cross sections of bWL cell device: a) CC contacts; b) parallel bWL; c) perpendicular bWL
Figure A.23 (a) Comparison of WL capacitances. (b) Comparison of BL capacitances.
Figure A.24 (a) Plot for Vt vs. Body bias. (b) SEM tilt image of Si active fin. (c) TEM image cut parallel to WL direction.
Figure A.25 Schematic cross-section view of a DGT cell array.
Figure A.26 (a) SEM cross-section parallel BL (b) SEM cross-section parallel WL
Figure A.27 (a) Transfer characteristic, comparison of simulation and measurement with 50μA/cell and 66mV/dev sub-threshold slope observed. (b) Measured off-current of SGT and controlled under 1fA/cell.
Figure A.28 Boundary, in the tSi - Na space, between partial and full depletion at the threshold of strong inversion calculated using the classical criterion of “critical band bending.”
Figure A.29 Electron concentration profile at constant gate voltage (VG=1V) for different values of semiconductor film thickness
Figure A.30 Dependence of the Vt. of the symmetrical double-gate (SDG) SOI structure on the semiconductor thickness [32].
Figure A.31 Bulk FinFET fin width versus threshold voltage and swing unit fin cell array transistor [45].
Figure A.32 shows Vt. dependence on silicon film thickness in a long channel, lightly-doped/undoped double gate transistor. The lower curve represents the classical consideration and the upper curve includes quantum-mechanical considerations.
Figure A.33 Effective electron mobility in SDG SOI transistor simulated by the “classical” and “quantum” models of the substrate region and the local mobility model [49].
Figure A.34 Measured effective electron mobility versus effective field with various silicon film thickness [50].
Figure A.35 Schematics of top view finfet under-lap structure
Figure A.36 Drain current characteristics of NMOS FinFETs with G-S/D overlap and under-lap predicted by Taurus-Medici: Lg=13nm, Wfin=7nm, Lext=10 nm, σS/D=4 nm/dec, midgap gate work function, and VDS=0.9 and 0.05V.
Figure A.37 (a) Transistor structures and energy-band diagrams for bulk-Si MOSFET and symmetrical DG-MOSFET [52]. (b). Energy band diagrams for n-type and p-type gate applications. BTBT is enhanced with the p-type gate at the same negative gate bias due to the built-in potential difference [53].
Figure A.38 (a) Doping profile and GIDL current as a function of source/drain ion implant processes. (b) The reduction of source/drain contact concentration can suppress GIDL and SCE at the same time. Appropriate trade-off between performance and GIDL is important for the selection of the doping level.
Figure A.39 Transverse electric field (y-axis) has been decreased, but the other electric field does not decrease in thinner fin. GIDL is decreased as the BTBT generation region reduces.
Figure A.40 The Id-Vg characteristics of GIDL for different junction process engineering. Selective Epitaxy Growth (SEG) can help to reduce the FinFET GIDL with proper optimization.
Figure A.41 (a) GIDL (Gate Induced Drain Leakage) and junction leakage of 1: FinFET with low VTC + NWL, 2: FinFET with VTC adjust implant, RCAT and planar transistor. (b) Transistor performance characteristics of RCAT, planar, and FinFET transistor (Lg=90nm) This FinFET shows excellent DIBL characteristics
Figure A.42 Array FinFET image with active WL and passing WL.
Figure A.43 (a) Illustrations of conventional, (b) damascene, and (c) local damascene FinFET structures are shown. For each figures, gates run on and along the buried damascene gates, which are not shown here for clear visual. (b) The
Figure A.44 shows the fabricated LD-FinFET structures. (a) Top view shows the damascene and gate patterns. (b) Vertical view along the gate line is shown. We can see the active fin structure. (c) Vertical view perpendicular to the gate lines.
Figure A.45 (a) Vt distributions of FinFET and SRCAT are compared. For Vbs=0V and –1V, the body effects are also shown. (b) Swing distributions for FinFET and SRCAT are plotted.
Figure A.46 shows the GIDL-Ioff correlation with and without junction broadening (JB). Junction broadening makes GIDL small but SCE becomes worse.
Figure A.47 Evolution of DRAM cell transistors.
Figure A.48 Id-Vg characteristics of RC FinFET show excellent SCE controllability.
Figure A.49 Structure of fabricated devices. (a) top view after recess formation, (b) vertical image perpendicular to word-line direction, (c) vertical image parallel to word-line direction.
Figure A.50 (a) Comparison of Vt vs Ion correlation. Ion of RC-FinFET is about 60% larger than RCAT. (b) Comparison of Subthreshold swing (SS) at 85℃. RC-FinFET has nearly ideal SS
Figure A.51 (a) GIDL–Ioff correlation. GIDL of RC-FinFET is about 50% smaller than LD-FinFET at the same Ioff. (b) Data retention characteristics of LD-FinFET and RC-FinFET at 85℃
Figure A.52 (a) Dependence of subthreshold swing and body bias effect (∆Vt) versus channel doping concentration. (b) Threshold voltage and junction leakage current (JLK) depending upon the channel doping concentration with Lg = 75 nm.
Figure A.53 (a) Simulated Ids as a function of Vth. Ids for Lg = 55 nm is seriously degraded by about 2.6 times compared with Lg = 75 nm. (b) Correlation of Vth vs. Ids. Ids of FinFET with SD-FO has 48 % superior to FinFET without SD-FO.
Figure A.54 Schematic view of SGT cell.
Figure A.55 Evolution of DRAM cell transistor structures.
Figure A.56 VPT array (a) Bird's-eye view which shows buried BL and isolation under pillar transistor, (b) layout of pillar shows different spaces between pillars which are 1.0F and 0.5F in WL and BL direction, respectively and (c) BL is formed self-aligned along BL direction by 0.25F oxide spacer formation.
Figure A.57 DRAM cells featuring vertical surrounding gate transistors (SGTs) as select device. Trench capacitor connected to the vertical channel by buried strap dopant diffusion junction.
Figure A.58 (a)+(b): Formation of a floating body by the lower S/D and depletion region. (c): A body contact is provided by a hole-accumulation layer generated by the proposed backside gate.
Figure A.59 Simulated storage node current of a floating body device caused by the transient bipolar effect (VBLH = 1.5 V).
Figure A.60 Transient characteristics of the storage node voltage are compared for a floating body device and a fully depleted SGT with body contact. The pulsed BL signal features a duty cycle of 99 % and a period of 10 ms (VBLH = 1.5 V). The capacitor charge is refreshed by a 1 µs WL pulse with a period of 100 ms (VWLL = -1 V, VWLH = 2 V)
Figure A.61 (a) Bird’s-eye view of FC-SGT (b) Equivalent circuit of FC-SGT DRAM cell.
Figure A.62 Physical models of soft errors in FC-SGT DRAM cells. (a) SOI structure suppresses minority carrier collection from substrate. (b) Electrons are collected to the storage node or BL. Holes are accumulated in the body region. (c) In a “0” state, electrons are transferred from the storage node to BL. (d) In a “1” state, electrons are transferred from BL to the storage node.
Figure A.63: Measured (circles) and simulated (lines) subthreshold slopes (a) and threshold voltages (b) of a fully depleted SGT with body contact. Simulated characteristics of a similar bulk SGT are shown for comparison.
Figure A.64 I-V curvet and sub-threshold characteristics of a 200nm SGT.
Figure A.65 (a) VPT simulation with impact ionization model applied. SCE became severe due to floating body effect. (1.8E13 cm2 channel dose and 60 nm thick pillars are used.) (b) Id-Vg curves of VPT for pillar thickness of 20 nm and 80 nm. The channel dose is 1.8E13cm-2.
Figure A.66 Vertical SEM images after (a) Si pillar trimming, gate oxidation, gate deposition and gate poly etching (b) buried BL formation (c) SEM of fabricated VPT array with N+ poly gate and WL.
Figure A.67 (a) VPT vertical SEM images after gate formation for different offset Si height, (b) 60 nm offset Si shows about 10 times decreased GIDL compared to 30 nm offset Si.
Figure A.68 (a) Dependence of the subthreshold slope on the silicon pillar thickness of the FC-SGT. (b) Parasitic bipolar current at 100 ps as a function of silicon pillar thickness. It is the source leakage current before the alpha-particle strike.
Figure A.69 (a) 8F2 trench DRAM cell [5] (b) 6F2 stacked DRAM cell [6]
Figure A.70 (a) The conceptual image of 6F2 (b) The comparison of s-poly node cross sectional image.
Figure A.71 Comparison of top view SEM images in active island and RCAT area.
Figure A.72 The FC-SGT DRAM cell. (a) birds-eye view, (b) cross-sectional view, (c) equivalent circuit, and (d) top view.

REFERENCES
[1]. Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin, “An Introduction to DRAM” in ”DRAM circuit design”, IEEE Press 2008 p1~31.
[2] Tae Kim, “Low voltage sensing scheme having reduced active power down standby current,” US Patent, 7,372,746 May 13, 2008.
[3] C. C. Chen, “Standby current reduction circuit applied in DRAM,” US patent, 6,775,194 Aug. 10, 2004.
[4] S. H. Jain et al., “Low resistance, low leakage ultra-shallow P+ junction formation using millisecond flash anneals” T-ED VOL 52 NO 7 p1610-1615 JULY 2005.
[5] T. Rupp, et al., “Extending Trench DRAM Technology to 0.15um Ground rule and Beyond” IEDM Technical Dig., 1999, pp. 33-36.
[6] F. Fishbum et al., “A 78nm 6F2 DRAM Technology for Multi-giga-bit Densities”, Symp. VLSI Tech. Dig., p28-29 (2004).
[7] Gutsche, M.; et al., “Capacitance enhancement techniques for sub-100 nm trench DRAMs” IEDM Technical Digest, pages:18.6.1 - 18.6.4., 2001.
[8]. J. Amon, et al., “A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology” in Proc. IEDM Tech. Dig., p.73-76, 2004
[9]. K. Kanba, et al., “A 7 Mask CMOS technology Utilizing Liquid Phase Selective Oxide Deposition” in Proc. IEDM Tech. Dig., 1991, P 637.
[10]. T. Homa et al., ”A New Interlayer Formation Technology For Completely Planarized Multilevel interconnection by using LPD” in Proc. VLSI Symp., vol. 2-2 p 3-4 1990.
[11]. Chihg-Fa Yah, and Chien-Hung Liu, “Applying Selective Liquid Phase Deposition to Create Contact Holes in Plasma Damage-Free Process“, 3rd International Symposium on Plasma Process-Induced Damage, P 223-226, 1998.
[12]. Ching-Fa Yeh, TZung-Zu Yuang, and Tai-Ju Chen ”Characterustucs if Self-Induced Lightly-Doped- Drain Polycrystalline Silicon Thin Film Transistors with Liquid-Phase Deposition SiO2 as Gate Insulator and Passivation-layer” IEEE Trans. Electron Device, VOL 42, NO 2, P 307, 1995.
[13]. Ching-Fa Yeh, Shyue-shyh Lin and Tzy-Yan Hong, “High Quality Thin Oxide Films Formed by Using Ultra Low Temperature Liquid Phase Deposition” Proc. EDMS, 11-21-78 1994.
[14] M.-K. Lee, C.-H. Lin, C.-N. Yang, and C.-D. Yang, “The improvement of liquid phase deposition of silicon dioxide with hydrocloric acid incorporation” Jpn J. Appl. Phys., vol. 37, pp L682-L683, 1998.
[15] C. F. Yeh, S –S Lin, C. L. Chen, and Y –C Yang. “Novel Technique for SiO2 Formed by Liquid-Phase Deposition for Low-Temperature Processed Polysilicon TFT” IEEE Electron Device Lett., vol. 14, NO. 8, pp. 403-405, 1993.
[16] J.A. Mandelman, et al., “Challenges and future directions for the scaling of dynamic random-access memory (DRAM) “IBM J. RES & DEV.vol. 46 NO. 2/3 MARCH/MAY 2002.
[17] Yuan Taur and Tak h. Ning, Fundamental of Modern VLSI Devices, Cambridge University Press, 1998.
[18] W. Skorupa et al., “Advanced Thermal Processing of Ultrashallow Implanted Junction Using Flash Lamp Annealing”, The Journal of Electrochemical Society (JECS) 152 (6) G436-G440 (2005).
[19] R. D. Chang, P. S. Choi, D. Wristers, and D. L. Kwong, “Experiments and Modeling of Boron Segregation in As Implanted Si During Annealing” IEDM Tech. Dig., 1997 p497.
[20] R. Kim et al., “Modeling of Arsenic Transient Enhanced Diffusion and Background Boron Segregation in Low-Energy As+ Implanted Si” IEDM Tech. Dig., 2000 p523.
[21] W. Lerch, et al., “Experimental and theoretical results of dopant activation by a combination of spike and flash annealing” IWJT 2007 P129-134
[22] S. H. Jain et al., “Low resistance, low leakage ultra-shallow P+ junction formation using millisecond flash anneals” T-ED VOL 52 NO 7 p1610-1615 JULY 2005.
[23] Th. Feudel et al., “Process integration issues with spike, flash, and laser anneal implementation for 90 and65nm technologies” 14th International Conference on Advance Thermal Processing of Semiconductors RTP-2006 p73-78.
[24] Yuan Taur and Tak H. Ning, “CMOS device design” in “Fundamental of Modern VLSI Devices,” Cambridge University Press. 1998 p164-223.
[25] K. Roy et al., “Leakage current mechanisms and leakage reduction techniques in deep-sub-micrometer CMOS circuits.” Proceeding of the IEEE, 91 305-327(2003).
[26] G. H. Buh, G. H. Yon, T. S. Park, J. W. Lee, J. Y. Kim, “Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub-50 nm Node DRAM,” IEDM Tech. Dig., Session-33.4, (2006).
[27] M. Chang et al., “Impact of Gate Induced Drain Leakage on Retention Time Distribution of 256Mbit DRAM with Negative Word line Bias” IEEE ED, VOL. 50, NO. 4, 1036-1041 April 2003.
[28] S. Zhao et al., “GIDL Simulation and Optimization for 0.13um/1.5V Low Power CMOS Transistor Design” SISPAD 2002 43-46.
[29] A. Cleverie et al., “Extended defects in shallow implants” Appl. Phys. A 76, 1025-1033 (2003).
[30] D. J. Eaglesham et al., “Implantation and transient B diffusion in Si: The source of the interstitials” Appl. Phys. Lett. 65(18), 31 Oct. 2305-2307 (1994).
[31] D. A. Neamen, “The pn Junction Diode” in” Semiconductor Physics & Devices: basic principles” MacGraw-Hill Companies, Inc. 1997 p 241-306.
[32] K. Uwasawa, T. Uchida, T.Ikezawa, M. Hane, T. Matsuke, H. Kato and K.Ishida, “A new boron diffusion model incorporating the dislocation loop growth” IEDM Tech. Dig. 1994 p873-876.
[33] R. Weis, and et al., “A Highly Cost Efficient 8F2 DRAM Cell with a Double Gate Vertical Transistor Device for 100 nm and Beyond” Tech. Digest of IEDM, pp. 415-418 (2001)
[34] R. Divakaruni et al., “Technologies for Scaling Vertical Transistor DRAM Cells to 70nm “ VLSI Tech Dig., 5B-2 (2003)
[35] S. M. Sze, “MOSFET Structure” in “Physics of Semiconductor Devices”, John Wiley and Sons, Inc. (1981), P490.
[36] J. Y. Kim et al., “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond,” VLSI Technical digest, pp.11-12, 2003.
[37] W.S. Lee et al.,” Analysis of data retention time of nano-scale DRAM and its prediction by indirectly probing the tail cell leakage current” IEDM 2004
[38] J. Y. Kim et al., “The excellent scalability of the RCAT (Recess-Channel-Array-Transistor) technology for sub-70nm DRAM feature size and beyond,” Symp. VLSI TSA Tech. Dig., p33-34 (2005).
[39] S.J. Ahn et al., “Novel DRAM Cell Transistor with Asymmetric Source and Drain Junction Profiles Improving Data Retention Characteristics”, VLSI Tech. Dig., pp 176-177, 2002
[40] Y. K. Park et al., “Fully Integrated 56nm DRAM Technology for 1Gb DRAM”, VLSI Tech. Dig., pp 190-191, 2007.
[41] W. Mueller et al., “Challenges for the DRAM Cell Scaling to 40nm” IEDM 2005.
[42] S. -W Chung et al., “Highly Scalable Saddle-Fin(S-Fin) Transistor for sub-50nm DRAM Technology”, VLSI Tech. Dig., T_05_01 2006.
[43] L. Heineck et al.,”A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond” Tech. Dig. IEDM, pp. 31-34 2007.
[44] T. Schloesser et al., “A 6F2 Buried Wordline DRAM Cell for 40nm and Beyond”, VLSI Tech. Dig., pp 809-812 2007.
[45] C. H. Lee et al., “Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and beyond”, VLSI Tech. Dig., pp 130-131 2004.
[46] T. Schloesser et al., “Highly Scallable Sub-50nm Vertical Double Gate Trench DRAM Cell”, Tech. Dig. IEDM (2004).
[47] Xuejie Shi; Man Wong, “Effects of substrate doping on the linearly extrapolated threshold voltage of symmetrical DG MOS devices”, IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005 Page(s):1616 – 1621
[48] Jean-Pierre Colinge, “ The SOI MOSFET” in “FinFETs and Other Multi-Gate Transistors” Springer 2008
[49] Majkusiak, B. et al., “Semiconductor thickness effects in the double-gate SOI MOSFET”, IEEE Transactions on Electron Devices, Volume 45, Issue 5, May 1998 Page(s):1127 – 1134
[50] Jin-Hyeok Choi et al., “Electron mobility behavior in extremely thin SOI MOSFET's”, IEEE Electron Device Letters, Volume 16, Issue 11, Nov. 1995 Page(s):527 - 529
[51] J.-W Yang, et al., “Highly Manufacturable Double-Gate FinFET With Gate- Source/Drain Underlap”, IEEE Transactions on Electron Devices, Volume 54, Issue 6, June 2007 Page(s):1464 – 1470
[52] Yang-Kyu Choi et al., “Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs”, Jpn. J. Appl. Phys. 42 (2003) pp. 2073-2076.
[53] Hyun-Sook Byun et al., “3-Dimensional Analysis on the GIDL Current of Body-tied Triple Gate FinFET”, Simulation of Semiconductor Processes and Devices, 2006 International Conference on Sept. 2006 Page(s):267 – 270.
[54]Yong-Sung Kim et al., “Local-Damascene-FinFET DRAM Integration with P+ doped-silicon gate Technology for sub-60nm Device Generation” Tech. Dig. IEDM (2005).
[55] Makoto Yoshida et al., “RC-FinFET (Recessed Channel FinFET) Cell Transistor Technology for Future Generation DRAMs” International Conference on Solid State Device and Materials (SSEM), 2007 pp 230~231.
[56] Deok-Hyung Lee et al., “Improved Cell Performance for sub-50nm DRAM with Manufacturable Bulk FinFET Structure”, VLSI Tech. Dig., pp 164-165 2007.
[57] K. Sunouchi et al., “A surrounding Gate Transistor (SGT) cell for 64/256M bit DRAMs” Tech. Dig. IEDM 1989.
[58] K. Kim, “Future memory technology: challenges and opportunities”, VLSI Tech. Dig., pp 5-9 2008.
[59] J.M.Yoon et al.,”A Novel Low Leakage Current VPT (Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40nm Technology”, Technical Digest 64th Device Research Conference 2006.
[60] F. Hoffmann et al., “Surrounding Gate Select Transistor for 4F2 stacked Gbit DRAM”, Tech. Dig. IEDM 2003.
[61] B. Goebel et al., “Fully Depleted Surrounding Gate Transistor (SGT) for 70nm DRAM and Beyond”, Tech. Dig. IEDM 2002.
[62] F. Matsuoka et al., “Numerical Analysis of Alpha-Particle-Induced Soft Errors in Floating Channel Type Surrounding Gate Transistor (FC-SGT) DRAM Cell” IEEE Electron Devices, VOL. 50, NO. 7, JULY 2003
[63] C. M. Hsieh, P. C. Murley, and R. R. O’breien, “A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices,” IEEE Electron Device Lett., vol. EDL–2, Apr. 1981.
[64] F. Matshoka et al., “Device Design Guidelines for FC-SGT DRAM Cells With High Soft-Error Immunity”, IEEE Trans. On Electron Devices, VOL. 52, NO. 6, JUNE 2005
[65] K. Ohta et al., “A QUADRUPLY SELF-ALIGNED MOS (QSA MOS) A NEW SHORT CHANNEL HIGH SPEED HIGH DENSITY MOSFET FOR VLSI” Tech. Dig. IEDM 25.5 1979
[66] H. J. Oh et al., “Digh-Density Low-Power-Operating DRAM Device Adopting 6F2 Cell Scheme with Novel S-RCAT Structure on 80nm Feature Size and Beyond.
[67] S.J. Lin and C. S. Lai et al., “A novel trench capacitor enhancement approach by selective liquid-phase deposition”, IEEE Transaction on Semiconductor Manufacturing. VOL 18 NO 4, November 2005.
[68] S. J. Lin and C. S. Lai et al., “Integration of Millisecond Flash annealing on CMOS Devices for DRAM Manufacturing”, Symposium VLSI-TSA Tech. Dig., T-65 p99-100 (2008)
[69] S.J. Lin and C. S. Lai et al., “Gate-induced drain leakage (GIDL) improvement for Millisecond Flash Anneal (MFLA) in DRAM Application”, IEEE Transaction on Electron Device (to be published in August 2009).
[70] S.J. Lin and C. S. Lai et al., “Junction Breakdown Improvement by using Millisecond Flash Anneal (MFLA) in DRAM Application “, Journal of Electrical Chemical Society (JECS) (paper submitting).