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研究生:陳進欽
研究生(外文):Chin-Chin Chen
論文名稱:可展延之GF(2m)乘法硬體架構
論文名稱(外文):Scalable Hardware Architectures for Computing Multiplications over GF(2m)
指導教授:盧而輝李秋瑩李秋瑩引用關係
指導教授(外文):E. H. LuC. Y. Lee
學位類別:博士
校院名稱:長庚大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
論文頁數:125
中文關鍵詞:心臟收縮乘法器可展延硬體架構
外文關鍵詞:Systolic MultiplierHankel Matrix-Vectorscalable architectureGaussian Normal BasisToeplitz matrix-vectorMontgomery
相關次數:
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摘要
在目前,有限場 GF(2m) 是研究錯誤控制編碼、密碼技術及數位信號處理的有效工具。有限場的重要運算包含加法、乘法以及求反元素運算。加法是非常簡單而且可使用互斥或(XOR)閘電路來實現,其他運算則比較複雜且耗費時間。空間複雜度一般皆隨場大小m值變大而變大,於是m值通常很大之密碼應用,硬體複雜度必然為重要考量因素。然為了能夠實現密碼系統於環境限制的地方;例如智慧型卡片或是行動電話,因此研究工作著重於有限場GF(2m)乘法運算之低複雜和可展延硬體架構設計。而求反元素運算是可由重復使用乘法演算來達成,於此更顯示乘法之重要性。由於GF(2m)的運算較一般GF(p)或GF(pm)簡單快速且系統硬體電路實現亦同,故舉凡二進位BCH碼(Binary BCH Code)之解碼、RS碼(Reed-Solomon Code)之編碼與解碼及在安全通信上數位信息的加密與解密,皆在GF(2m)中執行運算。顯而易見;GF(2m)的使用較多也較為重要。
此外,本文所提出之所有乘法器運算架構均有規則性、模組性以及僅局部互連能力,此性能使得這些架構是很適合實現於VLSI電路上。
Abstract
Finite (Galois) field GF(2m) has widely applied to error control coding and public-key cryptography. Important operations of finite fields are addition, multiplication and inversion. Addition is very simple and can be implemented using XOR gates circuit. The other operations are much more complex and time consuming. According to space complexity depends on the field size m, chip area will be the most important factor for cryptography application by implementing hardware in VLSI. Hence, to implement a cryptosystem in a constrained environment such as smart cards or mobile phones, this work focuses on the design of low-complexity and scalable hardware architectures for computing multiplications over GF(2m). Since inversion can be carried out by repeated multiply-squaring algorithms. Moreover, all the proposed architectures have regularity, modularity and local interconnection ability, making them highly appropriate for VLSI implementation.
指導教授推薦書……………………………...………………………….i
口試委員會審定書…………………………………...…………………ii
國家圖書館授權書……………………………………..………………iii
長庚大學授權書……………………………………..…………………iv
誌謝……………………………………………...……………………….v
中文摘要………………………………………………………………..vi
英文摘要…………………………………………………….………...vii
目錄……………………………………………...…………………….viii Chapter 1 Introduction….…………………………………..……………1
1.1 Background………………...………………………………...…1 1.2 Synopsis of dissertation……………………………..…………..5
Chapter 2 Preliminaries……………………...…………………………...7 2.1 Representation of elements in GF(2m)…………………….……7 2.2 Multiplication in polynomial basis over GF(2m)……………….8 2.3 Traditional Polynomial-Basis Multiplication Algorithm over
GF(2m)………………………………………………………....11 2.4 Traditional Montgomery multiplication over GF(2m)………...13 2.5 Toeplitz matrix-vector multiplication……….………………16 2.6 Gaussian normal basis multiplication… ……………………...19 2.7 Bit-parallel systolic Hankel multiplier…………………...…….22
Chapter 3 Low-Complexity Bit-Parallel Systolic Multipliers over
GF(2m)………………………………………………………..27 3.1 Introduction…………..………………………………………..27 3.2 Proposed Bit-Parallel Systolic Multiplier over GF(2m)………29 3.3 Modified Bit-Parallel Systolic Multiplier over GF(2m)………34 3.4 Time-space Complexity…………………….………………....41
Chapter 4 Scalable and Systolic Montgomery Multipliers over
GF(2m)………………………………………………………..45 4.1 Introduction…………………………………………................45 4.2 Scalable systolic Montgomery multiplier over GF(2m)………..49 4.3 Scalable systolic Montgomery multiplier over GF(2m) generated
by generalized equally-spaced polynomials……..………….57 4.4 Time-space complexity……………………..…………………60
Chapter 5 Scalable and Systolic Gaussian Normal Basis Multipliers over
GF(2m) Using Hankel Matrix-Vector Representation………68
5.1 Introduction…………………….……………………………68
5.2 Proposed scalable and systolic GNB multiplier architecture…71
5.2.1 LSD-first scalable multiplier………..………….…..……75
5.2.2 MSD-first scalable multiplier………..………..………79
5.3 Modified Scalable and systolic GNB multiplier over GF(2m)...81
5.4 Time-space complexity…………………..……………………85 Chapter 6 Conclusions and Future Research Work………………….....94
6.1 Summary and main contribution………………………………94
6.2 Discussion for future research………………………………96
References……………………………………………………...….……98








Tables of Contents
Table 2.1. The relationship between j and k for i=2……………………24
Table 3.1. The behavior results of A(x)B(x) over GF(25)……………36 Table 3.2. A comparison between the proposed multipliers and existed
multipliers over GF(2m)..........................................................38
Table 3.3. Details of gate counts………………………………………..43
Table 4.1. Comparison of scalable architecture and the related unscalable
(bit-parallel) architecture for systolic Montgomery multipliers over GF(2m)…........................................................................63
Table 4.2. Comparison of scalable architecture and the related digit-serial
architecture for systolic multipliers over GF(2m)…………….64
Table 5.1. Comparison of various systolic normal basis multipliers of
GF(2m)…………………………………………………….….88
Table 5.2. Total latency for type-1 and type-2 GNB multipliers over GF(2m).……………………………………………………….89
Table 5.3. Various digit-serial systolic multipliers over GF(2m)………………………………………………………..90
Table 5.4. Optimal normal basis of GF(2m) for various digit-serial multipliers…………………………...……………………….91











Figures of Contents
Fig. 2.1. Bit-parallel semi-systolic Toeplitz multiplier for m=5….…….18 Fig. 2.2. Detailed circuitry of the U-cell…………………………….….18 Fig. 2.3. The bit-parallel systolic Hankel multiplier…………….…..….25 Fig. 2.4. (a) The detailed circuit of the U-cell; (b) The detailed circuit of
the V-cell.……………………………………………….……...26 Fig. 3.1. The detailed graph of Eq. (3.6)………………………………..31 Fig. 3.2. The proposed type-1 bit-parallel systolic multiplier over
GF(2m)…………………………………………………………33
Fig. 3.3. The detailed circuit of the U-cell……………………………...34
Fig. 3.4. The type-2 bit-parallel systolic multiplier over GF(2m)……….39
Fig. 3.5. The detailed circuit for the V-cell……………………………..40
Fig. 3.6. The detailed circuit for the W-cell…………………………….40
Fig. 3.7. The detailed circuit for the Q-cell………………………..……41
Fig. 4.1. Scalable systolic Montgomery multiplier architecture over GF(2m)…………………………………………………………56
Fig. 4.2. Scalable systolic Montgomery multiplier architecture for irreducible GESPs.……………………....................................60
Fig. 4.3. Relationship between latency and selected digital size d for GF(2163)…................................................................................65
Fig. 4.4. Relationship between transistor count and selected digital size d
for GF(2163)…………………………………………………….65
Fig. 4.5. Time-area product via selected digital size d for GF(2163)……66
Fig. 5.1. The proposed scalable and systolic architecture for computing AB0……...................................................................................75
Fig. 5.2. The proposed LSD-first scalable systolic GNB multiplier over GF(2m)…………………………………………………………79
Fig. 5.3. The proposed MSD-first scalable systolic GNB multiplier over GF(2m)…………………………………………………………81
Fig. 5.4. The modified LSD-first scalable systolic GNB multiplier over GF(2m)…..................................................................................84
Fig. 5.5. Time-area complexity for various digit-serial multipliers over GF(2²³³)………………………………………………………..91
Fig. 5.6. Transistor count for various digit-serial multipliers over GF(2²³³)………………………………………
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