臺灣博碩士論文加值系統

晶片封裝製程中，金線偏移是常遇到的問題，因為目前封裝趨勢一直朝向微小型化、高腳數位化，使得金線接合間距更緊密，所以如何有效控制金線偏移過大是半導體封裝的課題。
因目前封裝材料主要仍以金線為主，如何降低金線材料成本，為本文所要探討的重點，而本文利用數值分析與龔氏方程式(Kung’s Equation)比較分析，研究橢圓形金線在長短軸比值、不同跨距及高度所得之橫向位移及偏移勁度，將所得結果進行比較分析，以研究使用較小金線線徑可節省之材料成本及造成偏移勁度影響。

Concerns about wire sweep and wire sag on the applications of the 3-dimensional packaging technology in the multi-chip module systems have been highly raised recently. Because the interconnection distance of the multi-chip modules is usually longer than that in single-chip system. As gold content accounts for the majority of bonding wire expense, wire diameter reduction is an effective way to reduce cost. However, it had been proved by authors’ previous studies that the smaller the wire diameter is used, the smaller the sweep stiffness of wire bond is. The lower sweep stiffness of the wire bond will always cause higher risk of wire sweep.
Graphically speaking, we know that two different types of ellipses: horizontal and vertical. A horizontal ellipse is short and fat if the major axis is horizontal. Similarly, a vertical one is tail and skinny if the major axis is vertical. From the bending point of view, the horizontal ellipse cross section of gold wire can provide larger bending stiffness than the horizontal ellipse cross section of gold wire does. In this study, we will utilize the advantages of an ellipse to increase the sweep stiffness of a wire bond without increase gold weight or cost. The numerical analysis of sweep stiffness of a wire bond versus different scales of ellipse diameter is conducted. The theoretical results of Kung’s equation are provided for comparison. Finally, the concept of equivalent diameter of ellipse is proposed for using smaller diameter of gold wire and to reduce the material cost in semiconductor packaging.

摘 要 i
Abstract ii
誌 謝 iii
目 錄 iv
圖 目 錄 vii
表 目 錄 x
符 號 說 明 xi
第1章 前言 1
1-1 概述 1
1-2 文獻回顧 5
1-2-1 晶片封裝演變概述 5
1-2-2 相關研究文獻回顧 10
1-3 研究動機 11
1-4 論文架構 12
第2章 基本理論 14
2-1 金線拖曳力 14
2-1-1 Lamb’s Model 14
2-1-2 Takaisi’s Model 15
2-1-3 Sherman’s Model 15
2-2 微金線機械性質 16
2-3 金線偏移勁度理論 18
2-3-1偏移勁度定義 18
2-3-2 Kung’s Equation 19
2-4 截面橢圓幾何形狀對偏移勁度影響 22
第3 章 數值分析 29
3-1 金線偏移數值分析 29
3-2 有限元素法 32
3-3 ANSYS模擬分析 34
第4 章 結果與討論 44
4-1 不同金線線徑所得到預測與數值比較分析 44
4-2 橢圓形金線在不同長短軸之比值影響分析 46
4-3 橢圓形金線在長短軸比值與跨距之影響分析 52
4-4 K&S不同金線材質圓形試片實驗 57
第5 章 結論與未來展望 64
5-1 結論 64
5-2 未來展望 66
參考文獻 67
附錄A 71

[1] 林佑儒，“IC封裝業覆晶技術晶圓切割製程參數設計之研究”碩士論文，逢甲大學，2006。
[2] 王慧中，“我國半導體產業競爭力之探討”，碩士論文，義守大學，2005。
[3] 何昇輝，"半導體封裝Q弧、S弧及M型弧之金線偏移分析與實驗，碩士論文，正修科技大學，2006。
[4] 龔皇光、黃柏裕，"金線偏移分析與實證"，中華民國第二十七屆全國力學會議，台灣、台南、國立成奶j學，2003。
[5] 龔皇光，黃柏文，陳鴻雄，"半導體封裝微金線之鬆弛及破斷性質分析與實證"，中華民國第二十一屆機械工程研討會，台灣、高雄、國立中山大學，2004.05
[6] 鐘文仁，陳佑任，”IC封裝製程與CAE應用”，全華科技圖書公司。
[7] 洪立群，”IC構裝製程中金線外型之預測”，碩士論文，國立成奶j學(1998)。
[8] 蘇厚合，”電子構裝中金線偏移分析”，碩士論文，國立成奶j學(2000)。
[9] 曾永裕，“IC封裝內金線偏移之研究”，碩士論文，國立成奶j學，2003。
[10] 林樹均，葉均蔚，劉增豐，李勝隆，"材料工程實驗與原理"，全華科技圖書公司。
[11] 龔皇光，黃柏文，陳鴻雄，"ANSYS 與電腦輔助工程分析"，全華科技圖書公司。
[12] 鐘文仁，李宜修，" IC 封裝製程金線偏移之最佳化分析的探討"，中國機械工程學會第15 屆全國學術研討會論文集，pp.667-674。
[13] 黃柏裕，"半導體封裝金線偏移分析與實證"，碩士論文，正修科技大學，2004。
[14] 郭志鴻，"半導體封裝金線幾何形狀對金線偏移之影響"，碩士論文，正修科技大學，2006。
[15] 羅正忠，”半導體製程技術導論”，台灣培生教育出版公司。
[16] A.A.O. Tay,K.S. Yeo, H.H.Wu and T.B. Lim,”Wire Bond Deformation during molding of IC packages”, Transactions of ASME, Vol. 177, pp.178-184(1995).
[17] A.A.O. Tay, K.S. Yeo,J.H. Wu and T.B. Lim,”Wirebond Dsformation During Molding of IC Package,Transactions of the ASME, Journal of Electronic Packaging, Vol.117, pp 14-19(1995).
[18] Sejin Han, K.K. Wang,”A Study on Wire Sweep in Encapsulation of Semicronductor Chips Using Simulated Expeeriments”, Transactions of the ASME, Journal of Electronic Packaging, Vol.117, pp178-184 (1995).
[19] Sejin Han, K.K. Wang,”Effect of Fillers on Wire Sweep in Semiconductor Chip Encapsulation”, IEEE Transactions on Components Package and Manufacturing Technology-Part B. Vol.18, pp744-750(1995).
[20] J.H. Wu, A.A.O. Tay,K.S. Yeo, and T.B. Lim, ”A Three-Dimensional Modeling of Wire Sweep Incorporating Resin Cure”, IEEE Transactions on Components Package and Manufacturing Technology-Part B. Vol.21, pp65-72(1998).
[21] L.T. Nguyen, “Wire bond behavior during molding operation of electronic packages”, Polymer Engineering and Science, Vol.28, No.14, pp.826-943 , 1998.
[22] ASM AB339, “Fully Automatic Gold Wire Ball Bonder”, ASM Technology Singapore Pte. Ltd ,2000.
[23] S.J. Han, Y.J. Huh, "A Study of Wire Sweep During Encapsulation of Semiconductor Chips", Journal of the Microelectronics and Packaging Society, Vol.7, No.4, pp.17-22 (2000).
[24] C.C. Pei, S.J. Hwang, ”Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect”, Journal of Electronic Packaging, Vol. 127, pp. 335-339 (2005).
[25] H.K. Kung, "The Analysis of The Bending and Twisting Moments Induced Sweep Deflection for Semiconductor Package Applications", Proceeding of the 7st Electronics Package Technology Conference, Singapore (2005).
[26] H.K. Kung, C.H. Kuo, S.H. Ho, "Effect of Bond Spans and Bond Heights on the Sweep Stiffness of Wire Bond for Semiconductor Wirebonding Technology", Proceeding of the 4st Microelectronics Technology and Applications (2006).
[27] Kulicke & Soffa "Material Manual "。