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研究生:鍾易霖
研究生(外文):Yi-Lin Chung
論文名稱:應用於三維積體電路之多階層電路分割演算法
論文名稱(外文):A Multilevel K-layer Partitioning Algorithm For Three Dimensional Integrated Circuits
指導教授:陳美麗陳美麗引用關係
指導教授(外文):Mely-Chen Chi
學位類別:碩士
校院名稱:中原大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:56
中文關鍵詞:K層分割三維積體電路分割矽穿孔
外文關鍵詞:Throughhree dimensional integrated circuits partition
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在本論文中,我們提出了一個多階層的電路分割演算法應用於三維積體電路的架構中。演算法是以multilevel的架構來對netlist進行連續地coarsen。在un-coarsening的過程中執行K階層電路分割的程序。目的為最小化矽穿孔(Through Silicon Via, TSV)的總數目同時也遵守各層面積的限制。各層面積為電路面積的總和加上矽穿孔(Through Silicon Via, TSV)所使用面積的總和再除以層數。將電路分割演算法應用於三維積體電路的架構。我們使用一個類似FM的資料結構並且應用critical net的分佈,因此在一個cell搬動完後對gain值的更新非常有效率。實驗數據顯示我們提出的演算法對於工業用的測試電路可以有效率地最小化TSV所使用的數目及得到比較小的area overhead。
In this paper, we propose a multilevel K-layer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A K-layer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Vias (TSV) while observing the area constraint for each layer. The area of each layer is the summation of circuit area and TSV area then divided by the number of layer. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify some critical net distributions such that after a cell move, the program may update gains very effectively. The experiments show that with the proposed algorithm can effectively produce good results with minimization the number of TSV and small total area overhead for the tested industrial cases.
目錄
中文摘要………………………………………………………………Ⅰ
英文摘要………………………………………………………………II
致謝……………………………………………………………………III
圖目錄…………………………………………………………………VI
表目錄………………………………………………………………VIII
第一章、 前言………………………………………………………1
第二章、 相關研究及背景介紹……………………………………4
2.1 Modified Hyperedge Coarsening (MHEC)演算法之簡介……4
2.2 FM演算法之簡介………………………………………………………6
第三章、 問題描述及定義…………………………………………………7
3.1 基本定義………………………………………………………………7
3.2 問題描述………………………………………………………………10
第四章、 演算法與程式流程………………………………………………12
4.1 程式流程………………………………………………………………12
4.2 演算法…………………………………………………………………13
4.2.1 Multilevel Coarsening Phase…………………………………15
4.2.2 Initial K-layer Partitioning Phase………………………15
4.2.3 K-layer Partitioning Phase…………………………………16
4.2.4 Multilevel Uncoarsening and refinement Phases………22
第五章、 實驗結果…………………………………………………………………………23
5.1 執行平台與程式語言…………………………………………………………………23
5.2 實驗結果………………………………………………………………………………23
第六章、結論與未來方向…………………………………………………………………42
6.1 結論……………………………………………………………………………………42
6.2 未來方向………………………………………………………………………………42
參考文獻……………………………………………………………………………………43

圖目錄

圖1-1: package層次、電路晶片層次及晶圓層次…………………………2
圖1-2 (a): Face-to-Face…………………………………………………2
圖1-2 (b): Back-to-Back…………………………………………………2
圖1-2 (c): Face-to-Back…………………………………………………2
圖2-1: Hyperedge Coarsening (HEC)………………………5
圖2-2: Modified Hyperdege Coarsening (MHEC)…………5
圖3-1: 3D ICs架構…………………………………………………8
圖4-1:程式流程圖……………………………………………………12
圖4-2:示意圖…………………………………………………………14
圖4-3:Multilevel K-layer partitioning pseudo code……14
圖4-4(a):F(Ni)大於1………..…………………………………………17
圖4-5-1(a):F(Ni)等於1且cell A 往上搬………………………………18
圖4-5-2(a):F(Ni)等於1且cell A 往上搬………………………………18
圖4-6-1(a):F(Ni)等於1且cell A 往下搬………………………………18
圖4-6-2(a):F(Ni)等於1且cell A 往下搬………………………………18
圖4-7-1(a):F(Ni)等於1且cell A 往上搬………………………………19
圖4-7-2(a):F(Ni)等於1且cell A 往下搬………………………………19
圖4-8:K-layer partitioning pseudo code…………………………21
圖4-9:Multiledel Uncoarsening pseudo code……………………22



表目錄
表5-1:測試電路資訊........…………………...…………………………23
表5-2(a):Circuit_1 multilevel coarsening 之結果.…………………...…24
表5-2(b):Circuit_2 multilevel coarsening 之結果…………………...…24
表5-2(c):Circuit_3 multilevel coarsening 之結果.…………………...…25
表5-2(d):Circuit_4 multilevel coarsening 之結果…………………...…25
表5-3:Number of Normalized Module at each Coarsen Level...……….26
表5-4(a):Circuit_1 : Cell distribution by number of pin……………..…26
表5-4(b):Circuit_1 : Net distribution by number of pin.....……………..27
表5-5(a):Circuit_2 : Cell distribution by number of pin……………..…27
表5-5(b):Circuit_2 : Net distribution by number of pin.....……………..28
表5-6(a):Circuit_3 : Cell distribution by number of pin…..……………28
表5-6(b):Circuit_3 : Net distribution by number of pin.…..……………29
表5-7(a):Circuit_4 : Cell distribution by number of pin……..…………29
表5-7(b):Circuit_4 : Net distribution by number of pin…..……………30
表5-8(a):Circuit_1 : Initial K-layer Partitioning 之結果....……………..31
表5-8(b):Circuit_2 : Initial K-layer Partitioning 之結果...……………..31
表5-8(c):Circuit_3 : Initial K-layer Partitioning 之結果....……………..31
表5-8(d):Circuit_4 : Initial K-layer Partitioning 之結果...……………..31
表5-9(a):Circuit_1 : K-layer Partitioning 之結果..……....……………..32
表5-9(b):Circuit_2 : K-layer Partitioning 之結果..……....……………..32
表5-9(c):Circuit_3 : K-layer Partitioning 之結果..……....……………..33
表5-9(d):Circuit_4 : K-layer Partitioning 之結果..……....……………..33
表5-10(a):Circuit_1 : K-layer Partitioning(rlo=0.9,rup=1.1)之結果...…..34
表5-10(b):Circuit_2 : K-layer Partitioning(rlo=0.9,rup=1.1)之結果...…..34
表5-10(c):Circuit_3 : K-layer Partitioning(rlo=0.9,rup=1.1)之結果...…..34
表5-10(d):Circuit_4 : K-layer Partitioning(rlo=0.9,rup=1.1)之結果...…..34
表5-11(a):Circuit_1 : K-layer Partitioning(rlo=0.85,rup=1.05)之結果.....35
表5-11(b):Circuit_2 : K-layer Partitioning(rlo=0.85,rup=1.05)之結果.....35
表5-11(c):Circuit_3 : K-layer Partitioning(rlo=0.85,rup=1.05)之結果.…35
表5-11(d):Circuit_4 : K-layer Partitioning(rlo=0.85,rup=1.05)之結果.…35
表5-12: 不同rlo、rup 在Circuit_4 中的結果.....……………………….35
表5-13(a):Circuit_1 :Initial K-layer Partitioning 之結果………………37
表5-13(b):Circuit_2 :Initial K-layer Partitioning 之結果………………37
表5-13(c):Circuit_3 :Initial K-layer Partitioning 之結果.………………37
表5-13(d):Circuit_4 :Initial K-layer Partitioning 之結果………………37
表5-14(a):Circuit_1 :K-layer Partitioning 之結果……...………………38
表5-14(b):Circuit_2 :K-layer Partitioning 之結果……...………………38
表5-14(c):Circuit_3 :K-layer Partitioning 之結果……...………………38
表5-14(d):Circuit_4 :K-layer Partitioning 之結果……...………………38
表5-15(a): rlo為0.95、rup為1.05 之結果(With Coarsening)……………39
表5-15(b): rlo為0.9、rup為1.1 之結果(With Coarsening)………………39
表5-15(c): rlo為0.85、rup為1.15 之結果(With Coarsening)……………39
表5-16(a): rlo 為0.95、rup 為1.05 之結果(Without Coarsening)………40
表5-16(b): rlo 為0.9、rup 為1.1 之結果(Without Coarsening)…………40
表5-16(c): rlo 為0.85、rup 為1.15 之結果(Without Coarsening)………40
表5-17(a): K -layer partitioning (with coarsen)之run time 及memory
usage.……………………………………………………………………41
表5-17(b): K -layer partitioning (without coarsen)之run time 及memory
usage.……………………………………………………………………41
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