臺灣博碩士論文加值系統

現今電子產品設計中，降低產品功率消耗是一個非常重要的課題。在降低功率消耗設計的研究中，多重電壓設計是一種重要且有效的設計方法，而本論文使用雙重電壓降低總功率消耗並且不損耗電路效能，但不同電壓之間必須置入電壓轉換器，會造成額外功率消耗以及電路面積過大問題，因此本論文將探討如何在效能限制下最佳化功率消耗以及電壓轉換器置入。
目前大部份多重電壓分配的演算法都有很好的功率消耗改善，然而現存演算法並無法實際處理電壓轉換器面積因素，在某些電路下雖然可以獲得很好的功率消耗降低結果，但卻需要置入大量的電壓轉換器使得電路面積違反制定規格，因此本篇論文將提出一個基於線性規劃法的雙重電壓分配演算法，有效的降低總功率消耗與總電壓轉換器面積，而此演算法也可延伸至多重電壓架構下。
在電路時序限制下最佳化功率消耗，與GECVS演算法[4]比較，我們可更進一步獲得最多5.46%的功率消耗改善，並且平均有16.31%的電壓轉換器總個數降低。而在電路效能與電壓轉換器面積限制條件下最佳化功率消耗，平均功率消耗改善依然比GECVS來的好，並且平均有22.92%的電壓轉換器個數改善。

Low power consumption is a very important issue in modern electronic design. The multiple supply voltage technique is a highly effective method to reduce the dynamic power consumption. This thesis uses dual supply voltage to reduce the total power consumption under the circuit performance constraint. To ensure that a circuit works correctly, level converters need to be inserted between the cells with different supply voltages. However, converters take extra power consumption and circuit area. In this thesis, we explore the problem of optimizing power consumption and level shifter insertion under the performance constraint.
Many existing multiple supply voltages (MSV) algorithms perform very well for power reduction. However, they do not handle the area issue of level shifters. In some cases, although one gets a superior result to reduce the power consumption, but many level shifters are added so that the circuit area will be over the specification. In this thesis, we present an
effective integer linear programming (ILP)-based dual supply voltages assignment approach to solve this problem. This approach also can be
extended to solve MSV assignment problem.
For the objective of power reduction under timing constraint, compared with the GECVS algorithm [4], the power consumption can be
further reduced up to 5.46% and the number of level shifters is improved by 16.31% on average by our approach. For the objective of power
reduction under constraints of both timing and area of level shifters, the average improvement of power consumption obtained by our algorithm is
still better than GECVS while reducing the number of level shifters by 22.92% on average.

第一章 緒論.........................................................1
1.1 研究背景........................................................1
1.2 研究目的........................................................4
1.3 全文架構........................................................8
第二章 相關研究背景介紹.............................................9
2.1 電壓轉換器探討低功率相關研究....................................9
2.2 效能限制下最小化功率消耗相關研究................................18
第三章 問題描述與定義...............................................27
3.1 問題描述........................................................27
3.2 基本定義........................................................28
第四章 演算法.......................................................30
4.1 目標( Objective )...............................................30
4.2 電壓源分配與電壓轉換器置入......................................31
4.3 電路效能與面積限制..............................................32
第五章 範例說明.....................................................35
5.1 目標( Objective )...............................................35
5.2 電壓源分配與電壓轉換器置入......................................36
5.3 電路效能與面積限制..............................................39
第六章 實驗結果.....................................................41
6.1 測試電路屬性....................................................41
6.2 測試結果........................................................42
6.3 結果分析........................................................45
結論................................................................48
參考文獻............................................................49
圖一：CMOS 反向器電路...............................................2
圖二：Multiple Supply Voltages Technique ...........................3
圖三：一般典型電壓轉換器( level shifter )設計.......................4
圖四：CVS 的結果範例................................................5
圖五：考慮電壓轉換器影響下最佳化功率消耗............................7
圖六：演算法的流程圖................................................10
圖七：計算delay 和power 合併不同模組的過程..........................11
圖八：不同的方法來描述模組的相鄰關係................................12
圖九：演算法的流程圖................................................16
圖十：傳統電壓轉換器................................................17
圖十一：該論文所提新的電壓轉換器....................................17
圖十二：兩臨界電壓的傳遞延遲和漏電流資訊............................19
圖十三：演算法的流程................................................20
圖十四：演算法的設計流程............................................23
圖十五：靈敏度的計算................................................24
圖十六：改良式的演算法..............................................25
圖十七：例說明延遲分配的作法........................................26
圖十八：電壓轉換器置入情況..........................................31
圖十九；使用兩變數塑造的timing arc function.........................33
圖二十：The timing arc of each input pin in the cell library........34
圖二十一：範例電路..................................................35
圖二十二：電路 C6288 結構...........................................44
圖二十三：功率消耗與電壓轉換器個數的取捨............................45
圖二十四：GECVS 與本論文不考慮面積條件演算法的比較結果..............46
圖二十五：GECVS 與本論文考慮面積條件演算法的比較結果................47
圖二十六：整數線性規劃變數與限制式的數量............................47
表格1：Benchmark 統計表.............................................42
表格2：本論文演算法與 GECVS 比較結果................................43
表格3：電壓轉換器面積花費限制影響...................................45

[1] H. Wu, M. Wong and I. Liu, “Timing-Constrained and
voltage-Island-Aware Voltage Assignment,” in Proc. of ACM/IEEE
Design Automation Conference, pp. 429-432, 2006.
[2] K. Usami and M. Horowitz, “Clustered Voltage Scaling Technique
for Low-Power Design,” in Proc. of ACM International Symposium
on Low Power Design, pp. 3-8, 1995.
[3] D. Monica, M. Luca, M. Alberto, M. Enrico, and P. Massimo,
“Enhanced Clustered Voltage Scaling for Low Power,” in Proc. of
the 12th ACM Great Lakes symposium on VLSI, pp. 18-23, 2002.
[4] S. H. Kulkarni, A. N. Srivastava, and D. Sylvester, “A New
Algorithm for Improved VDD Assignment in Low Power Dual
VDD Systems,” in Proc. of ACM International Symposium on Low
Power Design, pp.200-205, 2004.
[5] F. Dabiri, R. Jafari, A. Nahapetian, and M. Sarrafzadeh, “A Unified
Optimal Voltage Selection Methodology for Low-Power Systems,”
in Proc. of the ACM International Symposium on Quality
Electronic Design, pp. 210-218, 2007.
[6] Synopsis, Power Compiler User Guide, version B-2008.09.
[7] H. Zhou and D. F. Wong, “An Exact Gate Decomposition
Algorithm for Low-Power Technology Mapping,” in Proc. of the
IEEE/ACM International Conference on Computer-Aided Design,
pp.575-580, 1997.
[8] J.C. Chi, H.H. Lee, S.H. Tsai, and M.C. Chi, “Gate Level Multiple
Supply Voltage Assignment Algorithms for Power Optimization
Under Timing Constraint,” IEEE Transactions on Very Large Scale
Integration Circuits and Systems, pp. 637-648, 2007.
[9] B. Liu, Y. Cai, Q. Zhou, and X. Hong, “Power Driven Placement
with Layout Aware Supply Voltage Assignment for Voltage Island
Generation in Dual-Vdd Designs,” in Proc. of ACM/IEEE Asia and
South Pacific Design Automation Conference, pp. 582-587, 2006.
[10] D. Nguyen et al. “Minimization of Dynamic and Static Power
Through joint Assignment of Threshold Voltages and Sizing
Optimization,” in Proc. of ACM International Symposium on Low
Power Design, pp. 158-163, 2003.
[11] F. Brglez and H. Fujiwara, “A neural netlist of 10 combinational
benchmark circuits and a target translator in Fortran,” in Proc. of
IEEE International Symposium on Circuits and Systems, pp.
695-698, 1985.
[12] Dimitrios Soudris, C. Piguet, C. Goutis, Designing CMOS Circuits
for Low Power, Boston, MA :Kluwer Academic Press, 2002.
[13] V. Kursun and E. Friedman, Multi-Voltage CMOS Circuit Design,
John Wiley & Sons, Ltd, 2006.
[14] Bhanu Kapoor, Shankar Hemmady, Kaushik Roy, “SoC Power
Management Verification”, in tutorial of IEEE International
Conference of Computer Design, 2008.
[15] F. Aezinia and A.A. Kusha, “Low Power High Performance Level
Converter for Dual Supply Voltage Systems,” IEICE Electronics
Express, Vol 4, No. 9, pp. 306-311, 2007.
[16] G. Ankur, C. Rajat, M. Vinod, N. Vikas and H.M. Roopashree, “A
Robust Level-Shifter Design for Adaptive Voltage Scaling,” in
Proc. of IEEE International Conference on VLSI Design, pp.
383-388, 2008.
[17] C. Chen and M. Sarrafzadeh, “An Effective Algorithm for
Gate-Level Power-Delay Tradeoff Using Two Voltages,” in Proc.
of IEEE of International Conference on Computer Design, pp.
222-227, 1999.
[18] A.U. Diril, Y.S. Dhillon, A. Chatterjee and A.D. Singh,
“Level-Shifter Free Design of Low Power Dual Supply Voltage
CMOS Circuits Using Dual Threshold Voltages,” IEEE
Transactions on Very Large Scale Integration Systems, pp.
1103-1107, 2005.
[19] M. Ekpanyapong, P. Korkmaz, and S.K. Lim, “ILP-based Supply
and Threshold Voltage Assignment for Total Power Minimization,”
in Technique Report in Georgia Institute of Technology, pp.1 – 13,
2007.
[20] P. Elakkumanan, K. Thyagarajan, K. Prasad and R. Sridhar,
“Optimal Vth Assignment and Buffer Insertion for Simultaneous
Leakage and Glitch Minimization though Integer Linear
Programming (ILP),” in Proc. of IEEE International Midwest
Symposium on Circuits and Systems, pp.1880-1883, 2005.
[21] Pavel Ghosh and Arunabha Sen, “Energy Minimization using a
Greedy Randomized Heuristic for the Voltage Assignment Problem
in NoC,” in Proc. of IEEE Interntaional SOC Conference,
pp.78-84, 2008.
[22] Y.H. Huang, P.Y. Chen, and T.T. Hwang, “Switching-Activity
Driven Gate Sizing and Vth Assignment for Low Power Design,”
in Proc. of ACM/IEEE Asia and South Pacific Design Automation
Conference, pp.576-581, 2006.
[23] M. Hamada, Y. Ootaguro, and T. Kuroda, “Utilizing Surplus
Timing for Power Reduction,” in Proc. of IEEE Custom Integrated
Circuits Conference, pp. 89–92, 2001.
[24] F. Ishihara, F. Sheikh and B. Nikolic, “Level Conversion for
Dual-Supply Systems,” IEEE Transactions on Very Large Scale
Integration Systems, pp. 185-195, 2004.
[25] P. Kapur, G. Chandra and K. C. Saraswat, “Power Estimation in
Global Interconnects and its Reduction Using a Novel Repeater
Optimization Methodology,” in Proc. of ACM/IEEE Design
Automation Conference, pp. 461-466, 2002.
[26] Q.A. Khan, S.K. Wadhwa, K.Misri, “A Single Supply Level Shifter
for Multi-Voltage Systems,” in proc. of International Conference
on VLSI Design held jointly with 5th International Conference on
Embedded Systems Design, pp. 557-560, 2006.
[27] W.P. Lee, H.Y. Liu and Y.W. Chang, “Voltage island aware
floorplanning for power and timing optimization,” in Proc. of
IEEE/ACM International Conference on Computer-Aided Design,
pp. 389--394, 2006.
[28] W.P. Lee, H.Y. Liu, and Y.W. Chang, “An ILP algorithm for
post-floorplanning voltage-island generation,” in Proc. of
IEEE/ACM International Conference on Computer-Aided Design,
2007.
[29] Q. Ma and F.Y. Young, “Voltage Island-Driven Floorplanning,” in
Proc. of the IEEE/ACM International Conference on
Computer-Aided Design, pp.644-649, 2007.
[30] W.K. Mak and J.W. Chen, “Voltage Island Generation under
Performance Requirement for SoC Designs,” in Proc. of
ACM/IEEE Asia South Pacific Design Automation Conference, pp.
798–803, 2007.
[31] J. Mi, C. Chen and H.K. Kwan, “Power-Oriented Delay Budgeting
for Combinational Circuits,” in Proc. of IEEE International
Symposium on Circuits and Systems, pp. 3033-3036, 2006.
[32] M.S.E. Sendi and I.R. Gatabi, “Improved Low Voltage All Cascode
Mirror Current Source Using the DC Level Shifter,”in Proc. of
IEEE International Midwest Symposium on Circuits and Systems,
pp.171-172, 2005.
[33] W.T. Shiue, C. Chakrabarti, “Low-Power Scheduling with
Resources Operating at Multiple Voltages,” in IEEE Transactions
on Circuits and Systems—II: Analog And Digital Signal Processing,
pp.536-543, 2000.
[34] A. Srivastava and D. Sylvester, “Minimizing Total Power by
Simultaneous Vdd/Vth Assignment,” in Proc. of ACM/IEEE Asia
and South Pacific Design Automation Conference, pp.400-403,
2003.
[35] K.H. Tam and L. He, “Power Optimal Dual-Vdd Buffered Tree
Considering Buffer Stations and Blockages,” in Proc. of
ACM/IEEE Design Automation Conference, pp. 497-502, 2005.
[36] C.Q. Tran, H. Kawaguchi and T. Sakurai, “Low-Power High-Speed
Level Shifter Design for Block-level Dynamic Voltage Scaling
Environment,” International Conference on Integrated Circuit
Design and Technology, pp. 229-232, 2005.
[37] K.L. Tsai, J.Y. Lee, S.J. Ruan and F.P. Lail, “Low Power
Scheduling Method using Multiple Supply Voltages,” in Proc. of
IEEE International Symposium on Circuits and Systems, pp.
5295-5298, 2006.
[38] Y.J. Yeh and S.Y. Kuo, “An Optimization-Based Low-Power
Voltage Scaling Technique Using Multiple Supply Voltage,” in
Proc. of IEEE International Symposium on Circuits and Systems,
pp. 535-538, 2001.
[39] B. Zhang, L.P. Liang, X.G. Wang, ”A New Level Shifter with Low
Power in Multi-Voltage System,” in Proc. of IEEE International
Conference on Solid-State and Integrated Circuit Technology,
pp.1857-1859, 2006.