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研究生:廖方晨
研究生(外文):Fang-Chen Liao
論文名稱:設計一個針對多核心系統之互聯網路的高度可擴充機制
論文名稱(外文):Design A Highly Scalable Mechanism for The Interconnection Network of the Multi-core System
指導教授:朱守禮
指導教授(外文):So-Li Chu
學位類別:碩士
校院名稱:中原大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:54
中文關鍵詞:互聯網路多核心CrossbarOpenSPARC T1
外文關鍵詞:Interconnection NetworkMulti-coreCrossbarOpenSPARC
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藉由互聯網路(Interconnection Network,IN)架構來改善整體系統效能,將成為未來多核心電腦中關鍵的一環。其中Crossbar為互聯網路的主要架構之一。然而,在核心數大於16的多核心系統中,Crossbar會因為其擴充性及硬體成本而不再適用。故在這篇論文中,我們基於OpenSPARC 的環境提出了一個互聯機制的可行性研究。為了實現這個目標,我們的研究歷經以下兩個階段:首先,為了改寫OpenSPARC T1的互聯網路架構,我們針對其原始碼進行深入的探討。至於第二階段的部份,則採用OpenSPARC T1原有的迴歸(Regression)環境來驗證我們所提出的互聯機制。實驗結果顯示,我們針對多核心系統所提出的互聯機制確實是可行且成功的。
Improving the whole system performance by Interconnection Network (IN) architecture plays the critical role in many future multi-core computers. Crossbar is one of the principal architectures of IN. However, the crossbar will be not applicable due to its scalability and hardware cost in a multi-core (>16) system. In this paper we present a feasibility study of interconnection mechanism based on the OpenSPARC environment. Towards this purpose, the study goes through two phases. First, we conduct a detailed study of the OpenSPARC source code in order to rewrite its IN architecture. Second, we adopt the original regression environment of the OpenSPARC to verify our proposed interconnection mechanism. The experimental results show our mechanism is feasible and successful for multi-core systems.
摘要........................................................................................................................i
Abstract ................................................................................................................ii
致 謝..................................................................................................................iii
目錄......................................................................................................................iv
圖目錄..................................................................................................................vi
表目錄..................................................................................................................ix
第一章 緒論....................................................................................................... 1
1-1 簡介.................................................................................................................. 1
1-2 多核心處理器架構.......................................................................................... 1
1-2-1 同質性多核心處理器架構........................................................................... 1
1-2-2 異質性多核心處理器架構........................................................................... 2
1-3 研究動機.......................................................................................................... 5
1-4 論文架構.................................................................................................. 5
第二章 相關研究................................................................................................. 6
2-1 STI Cell..................................................................................................... 6
2-2 ARM MPCore........................................................................................... 8
2-3 UltraSPARC T1 ........................................................................................ 9
2-4 MIT RAW............................................................................................... 11
第三章 背景技術............................................................................................... 13
3-1 OpenSPARC T1 概述............................................................................. 13
3-2 CPU-Cache Crossbar.............................................................................. 14
3-3 CPU-Cache Crossbar 的傳輸................................................................. 18
第四章 具可擴充性的多核心系統之互聯網路架構....................................... 22
4-1 具可擴充性的互聯網路架構...................................................................... 23
4-2 具可擴充性的互聯網路之傳輸.................................................................... 25
4-2-1 互聯網路之PCX 介面及其傳輸............................................................... 25
4-2-2 互聯網路之CPX 介面及其傳輸............................................................... 26
4-3 Relay 模組之架構.......................................................................................... 28
4-3-1 Relay 模組要求的轉換機制....................................................................... 29
4-3-2 Relay 模組於PCX 中的傳輸..................................................................... 29
4-3-3 Relay 模組於CPX 中的傳輸..................................................................... 31
第五章 實驗結果............................................................................................... 34
5-1 迴歸測試........................................................................................................ 34
5-2 迴歸測試結果................................................................................................ 35
第六章 結論....................................................................................................... 37
參考文獻............................................................................................................. 38
附錄一:組態一的迴歸測試結果..................................................................... 40
附錄二:組態二的迴歸測試結果..................................................................... 41
附錄三:迴歸測試範例:wdr_tlb.s................................................................. 42


圖目錄
圖1-1 處理器與記憶體之效能差距.................................................................. 1
圖1-2 Video-coding 的多處理器系統架構........................................................ 2
圖1-3 MPOC 的多處理器系統架構................................................................... 2
圖1-4 Viper 多處理器系統架構.......................................................................... 3
圖1-5 Daytona 多核心數位訊號處理器架構..................................................... 4
圖1-6 OMAP 多核心處理器架構....................................................................... 4
圖2-1 Cell 處理器之區塊圖................................................................................ 6
圖2-2 Cell 處理器之元件互聯匯流排................................................................ 7
圖2-3 Cell 處理器之圓形環互聯網路架構........................................................ 8
圖2-4 ARM MPCore 處理器............................................................................... 9
圖2-5 UltraSPARC T1 處理器........................................................................... 10
圖2-6 UltraSPARC T1 處理器之區塊圖........................................................... 11
圖2-7 RAW 之區塊圖........................................................................................ 12
圖3-1 OpenSPARC T1 處理器......................................................................... 13
圖3-2 CCX(CPU-Cache Crossbar,CCX)................................................... 14
圖3-3 CCX 分為PCX 與CPX 兩部份............................................................. 15
圖3-4 處理器核心透過PCX 對L2 Banks、I/O 橋接器、浮點運算單元進行
存取..................................................................................................................... 16
圖3-5 CPU0 的封包在PCX 仲裁器中的資料路徑......................................... 17
圖3-6 L2 Banks、I/O 橋接器、浮點運算單元透過CPX 對各處理器核心進行
回傳..................................................................................................................... 17
圖3-7 PCX 封包傳送的時序圖,傳輸一個封包的要求................................. 19
圖3-8 PCX 封包傳送的時序圖,傳輸兩個封包的要求................................. 20
圖3-9 CPX 封包傳送的時序圖,傳輸一個封包的要求................................. 21
圖3-10 CPX 封包傳送的時序圖,傳輸兩個封包的要求............................... 21
圖4-1 跨兩叢集的連接..................................................................................... 22
圖4-2 跨多叢集的連接..................................................................................... 22
圖4-3 具可擴充性的互聯網路架構................................................................ 23
圖4-4 跨叢集架構 – 往前傳輸...................................................................... 23
圖4-5 跨叢集架構 – 往後傳輸....................................................................... 24
圖4-6 跨叢集傳輸的PCX 第一階段............................................................... 26
圖4-7 跨叢集傳輸的PCX 第二階段................................................................ 26
圖4-8 跨叢集傳輸的CPX 第一階段............................................................... 27
圖4-9 跨叢集傳輸的CPX 第二階段............................................................... 28
圖4-10 Relay 模組於PCX 介面中的Slave 與Master 介面........................... 29
圖4-11 Relay 模組於PCX 介面之狀態轉移................................................... 31
圖4-12 Relay 模組於CPX 介面中的Slave 與Master 介面........................... 32
圖4-13 Relay 模組於CPX 介面之狀態轉移................................................... 33
圖5-1 OpenSPARC 之迴歸測試的流程........................................................... 34
圖5-2 組態一(架構7_1):僅一顆處理器位於cluster2.................................. 35
圖5-3 組態二(架構6_2):有兩顆處理器位於cluster2.................................. 35


表目錄
表3-1 PCX 封包格式........................................................................................ 26
表3-2 CPX 封包格式........................................................................................ 28
表3-3 CCX 傳輸的管線化(pipeline)階段......................................................... 19
表5-1 組態一的測試檔案列表......................................................................... 35
表5-2 組態二的測試檔案列表......................................................................... 36
表5-3 迴歸測試結果......................................................................................... 36
表5-4 本地端叢集的存取週期......................................................................... 37
表5-5 跨叢集的存取週期................................................................................. 37
參考文獻

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