臺灣博碩士論文加值系統

在本論文中，我們提供一種選擇正反器(DFF)的方法，使電路可在部份掃瞄設計下，進行轉態延遲障礙(transition delay fault, TDF)的測試。除了在測試時可有較低的功率消耗(Power dissipation)，並有較高的障礙涵蓋率(fault coverage)。此種方法係依據正反器輸出入端之可控制性(controllability)與可觀察性(observability)，挑選正反器加入掃描鍊。另外設計在測試過程中，將沒有加入掃描鍊的正反器用另一條時脈訊號來控制，達到freeze電路的能力。由ISCAS’89標準測試電路的實驗結果中可知，此種技術可以有效的降低在平移週期與抓取週期之平均功率與峰值功率，同時也提供了比全掃瞄鍊設計更高的LOC(Launch-On-Capture)轉態障礙涵蓋率與較低的硬體面積負擔。

In this thesis, we propose a method of selecting partial flip-flops for testing transition delay faults. As compared to full-scan design, this partial-scan method can achieve higher fault coverage and lower testing power. Scan flip-flops are selected based on controllability and observability of input signals and output gates of flip-flops. The non-scan flip-flops are controlled by another clock to freeze partial circuit during shift operation of scan testing. Experimental results on ISCAS89 benchmarks show that the proposed technique can reduce both average and peak power in shift and capture cycle than full-scan design. In addition, the method can also provide higher LOC transition fault coverage and utilize lower area overhead.

中文摘要...................................................................................... Ⅰ
Abstract....................................................................................... Ⅱ
致謝........................................................................................... Ⅲ
目錄........................................................................................... IV
圖目錄...................................................................................... VI
表目錄....................................................................................... VIII
第一章 導論...............................................................................1
1-1研究動機與目標.............................................................1
1-2貢獻與成果簡述.............................................................2
1-3論文架構.........................................................................3
第二章 背景與相關研究...................................................4
2-1功率消耗.....................................................................5
2-1-1 切換功率消耗………………………………………….5
2-1-2 短路功率消耗………………………………………….7
2-1-3 功率分析流程………………………………………….8
2-2 掃描架構...................................................................10
2-2-1 全掃瞄架構…………………………………………...11
2-2-2 部分掃描架構………………………………………...12
2-3轉態故障模型.............................................................................14
2-4 可測分析………………………………………………...…….17
2-4-1 可控制性與可觀察性運算…………………………...17
2-4-2 序向元件之可控制性與可觀察性運算……………...18
2-5 相關研究…………………........................................................20
2-5-1 全掃瞄低功率設計方法………………....…………...20
2-5-2 部分掃瞄低功率設計方法…………………………...27
第三章 演算法與實作方法..................................................................33
3-1 部份掃瞄架構……………………………................................33
3-2 可控制性與可觀察性................................................................33
3-3 其它輸入可控制性值之總和....................................................35
3-4 掃描正反器選擇方法…………………………………………38
第四章 實驗流程與結果分析..............................................................41
4-1實驗流程…………………………………………….…………41
4-2實驗結果……………………………………………………….43
第五章 結論..........................................................................................58
參考文獻..................................................................................................59



圖目錄
圖 1. 負載電容充電路徑……………………….........…......…………..6
圖 2. 負載電容放電路徑………………………………...............……..6
圖 3. 短路電流路徑…………………………………….....…..........…..7
圖 4. 使用VCD file之PrimePower功率模擬…...………..............……..9
圖 5. DFF取代為Scan DFF…………..........………......…....….......…..10
圖 6. 全掃瞄架構………………………………………...............……12
圖 7. 單條時脈的部份掃瞄架構……………….......……........………13
圖 8. 兩條時脈的部份掃瞄架構…………….......………........………13
圖 9. Slow-to-Fall轉態故障之測試範例………………................……14
圖 10. Timing Diagram of Launch-on-Shift…….....………..............….15
圖 11. Timing Diagram of Launch-on-Capture……...…................……16
圖 12. AND閘之可測性分析舉例…………………….........….........…17
圖 13. D型正反器之可測性分析舉例…………......….........…………19
圖 14. J-scan DFF……………………….........……......………..……21
圖 15. Jump-scan chain (scan mode only)…………...............….....…22
圖 16. 信號機率……………………...........…………....………….….23
圖 17. X-Fill流程圖…………………….........….………...….….…..24
圖 18. low power ATPG流程圖………….......……………........…....25
圖 19. low power 掃瞄架構……………….…..............…………......26
圖 20. 掃瞄架構時脈安排圖…………………..............……………..26
圖 21. test clock module.........................................................................26
圖 12.a NTC = 41……………………………..............….…………..27
圖 22.b NTC = 37………………………………......……..........…….28
圖 22.c NTC = 35………………………………....................…………29
圖 23. 切割電路演算法………………......………….........…………..30
圖 24. 切割電路範例……………………......….........………………..30
圖 25. 時脈安排………………………………………....…...........…..30
圖 26. The example of s27…………….................……………….……31
圖 27. 部份掃瞄架構設計之一例.........................................................34
圖 28. 部分掃描之時脈安排.................................................................34
圖 29. 範例電路.....................................................................................36
圖 30. 部分掃瞄設計流程圖(Flow Chart)............................................38
圖 31. 範例狀態圖................................................................................40
圖 32. 實驗流程圖.................................................................................41
圖 33. 修改Timing..................................................................................42
圖 34. 修改Procedures..........................................................................42


表目錄
表 1. 測試功率與操作功率比較…………………….…...............…….1
表 2. 全掃描轉態障礙涵蓋率、測試涵蓋率與ATPG 效率................45
表 3. 部份掃描轉態障礙涵蓋率、測試涵蓋率與ATPG 效率............45
表 4. 平移週期之平均功率消耗...........................................................47
表 5. 平移週期之峰值功率消耗...........................................................48
表 6. 抓取週期之平均功率消耗...........................................................49
表 7. 抓取週期之峰值功率消耗...........................................................50
表 8. 1條時脈與2條時脈之測試功率消耗...........................................51
表 9. 1條時脈與2條時脈之轉態障礙涵蓋率.......................................52
表 10. 抓取週期之平均功率消耗文獻比較........................................53
表 11. 抓取週期之峰值功率消耗文獻比較........................................54
表 12. 抓取與平移週期之功率消耗文獻比較....................................55
表 13. 掃描鍊比率與面積比.................................................................56
表 14. 掃描鍊比率與面積增加比.........................................................56

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