本論文提出一種適用於心電圖訊號擷取的抗電源60-Hz干擾的帶拒濾波器。第一部分為一個高共模拒斥比以及低雜訊的轉導放大器，主要應用於生醫訊號雜訊的消除，此轉導放大器使用MIMOS 0.35µm與TSMC 0.35µm的模型模擬並比較，並以TSMC製程完成下線。
本研究所設計之轉導放大器佈局前模擬之共模拒斥比分別為138.28dB與137.34dB(MIMOS與TSMC)，TSMC佈局後模擬之共模拒斥比為135.74dB。在雜訊邊限的部份，MIMOS與TSMC佈局前模擬分別為2.87mV2/Hz與486.90nV2/Hz，TSMC之佈局後模擬為488.26nV2/Hz。與本研究前一代之轉導放大器相比，此轉導放大器有較高的88.34dB之增益，86.34度的高相位邊限與2.64V的輸入共模範為，此OTA晶片面積為101 x 256 um2(不含PAD)、788 x 814 um2(含PAD)。本下線晶片以完成量測，輸出百幅為+1.65V~-1.65V，共模輸入範圍為2.43V。
此轉導放大器應用於抗電源60-Hz干擾的帶拒濾波器，一般之作法是使用電阻與電容之被動元件所構成之雙T帶拒濾波器，本論文也模擬此電路特性，其中心帶拒頻率為60.11Hz與-60 dB之衰減，Q值為0.25。本論文是使用靴帶雙T結構之濾波器，Q值增加為3.48，此為雙T結構之13.92倍。
由於此濾波器需整合在晶片中，而電阻又暫大部分的晶片面積，因此本論文使用切換式電容來等效電阻，四種切換式電容電阻皆已測試完成，包含並聯結構、串聯結構、串並結構與雙線性切換式電容電阻結構，並透過此切換式電容電阻以及外接之時脈訊號來完成本論完的濾波器晶片之設計。

A 60-Hz notch filter is designed to minimize the power line interference on electrocardiograph signals. A high CMRR and low noise operational transconductance amplifier was first designed which are major parameters for noise elimination on biomedical signals. The OTA was fully tested on all process corners for both MIMOS 0.35µm and TSMC 0.35µm technology and was fabricated using TSMC 0.35µm technology.
The OTA has a CMRR of 138.28dB and 137.34dB for MIMOS and TSMC pre layout simulation respectively. TSMC post layout simulation shows a CMRR of 135.74dB. The noise margin on the other hand has a value of 2.87mV2/Hz and 486.90nV2/Hz for MIMOS and TSMC pre layout simulation respectively and as high as 488.26nV2/Hz for TSMC post layout simulation. In comparison with previously developed OTAs, the designed OTA has a high AC gain of 88.34dB, a high phase margin of 86.34o and ICMR of 2.64V. The OTA has a layout area of 101 x 256 um2 without the bonding pads and 788 x 814 um2 with bonding pads. The OTA chip was tested and testing results shows an output swing of -1.65V to +1.65V and ICMR of 2.43V.
The designed high CMRR and low noise OTA was used in the design of the 60-Hz notch filter. The commonly used RC Twin T notch filter configuration was used in the initial design of the with its center frequency at 60.11Hz. It has an attenuation of -60 dB and a Q factor of 0.25. A bootstrapped Twin T configuration was then designed in order to increase the Q factor of the notch filter. The additional resistor in conventional bootstrapped Twin T was eliminated and was replaced by a single transistor thus having the possibility for chip implementation. The bootstrapped Twin T has a Q factor of 3.48 which is 13.92 times as that of unaided Twin T configuration. The Q of the bootstrapped Twin T is adjusted through the size of the transistor.
The large resistor component for the RC Twin T notch filter was replaced with its switched capacitor equivalent. All four switched capacitor resistor equivalent configuration was tested – parallel, series, series-parallel and bilinear switched capacitor configuration. Through the use of switches, capacitors and an external clock, resistors can be replaced thus providing the possibility of chip implementation.

摘 要......................................................................................................................................... I
ABSTRACT .............................................................................................................................. II
ACKNOWLEGEMENT...........................................................................................................IV
TABLE OF CONTENTS...........................................................................................................V
LIST OF FIGURES...............................................................................................................VIII
LIST OF TABLES.................................................................................................................XIV
CHAPTER 1. INTRODUCTION..........................................................................................1
CHAPTER 2. REVIEW OF RELATED LITERATURE.......................................................4
2.1 Electrocardiograph Signal ......................................................................................4
2.2 Power Line Interference .........................................................................................5
2.3 Analog Filter...........................................................................................................8
2.3.1 Low Pass Filter ......................................................................................................... 9
2.3.2 High Pass Filter........................................................................................................11
2.3.3 Band Pass Filter .......................................................................................................11
2.3.4 Band Stop Filter ...................................................................................................... 13
2.3.5 All Pass Filter ......................................................................................................... 15
2.4 Switched Capacitor Filters....................................................................................15
2.5 Operational Amplifier...........................................................................................17
2.6 Table of Comparison ............................................................................................22
CHAPTER 3. OPERATIONAL TRANSCONDUCTANCE AMPLIFIER.........................24
3.1 Design Methodology ............................................................................................24
3.2 Simulation Results................................................................................................26
3.3 Post Layout...........................................................................................................28
3.4 Chip Testing..........................................................................................................30
CHAPTER 4. 60 HZ NOTCH FILTER...............................................................................33
4.1 Twin T Notch Filter ..............................................................................................33
4.2 Bootstrapped Twin T ............................................................................................35
4.3 Switched Capacitor Resistor Equivalent ..............................................................37
4.3.1 Parallel Configuration............................................................................................. 37
4.3.2 Series Configuration ............................................................................................... 39
4.3.3 Series-Parallel Configuration.................................................................................. 41
4.3.4 Bilinear Configuration ............................................................................................ 42
CHAPTER 5. CONCLUSION AND RECOMMENDATIONS..........................................46
REFERENCES........................................................................................................................48
APPENDIX A: OTA MIMOS 0.35μM PRE SIMULATION...................................................51
APPENDIX B: OTA TSMC 0.35μM PRE SIMULATION .....................................................61
APPENDIX C: OTA TSMC 0.35μM POST SIMULATION ...................................................71
APPENDIX D: ADV2P4M35 127B TAPEOUT CIC REVIEW FEEDBACK........................81
APPENDIX E: SWITCHED CAPACITOR SIMULATION....................................................91
E.1 Parallel Configuration ................................................................................................91
E.1.1 Parallel Switched Capacitor Resistor Equivalent ....................................................... 91
E.1.2 Twin T with Parallel Switched Capacitor Resistor Equivalent................................... 92
E.1.3 Bootstrapped Twin T with Parallel Switched Capacitor Resistor Equivalent ............ 94
E.2 Series Configuration...................................................................................................97
E.2.1 Series Switched Capacitor Resistor Equivalent.......................................................... 97
E.2.2 Twin T with Series Switched Capacitor Resistor Equivalent ..................................... 98
E.2.3 Bootstrapped Twin T with Series Switched Capacitor Resistor Equivalent............. 101
E.3 Series-Parallel Configuration ...................................................................................103
E.3.1 Series-Parallel Switched Capacitor Resistor Equivalent .......................................... 103
E.3.2 Twin T with Series-Parallel Switched Capacitor Resistor Equivalent...................... 104
E.3.3 Bootstrapped Twin T with Series-Parallel Switched Capacitor Resistor Equivalent 107
F.4 Bilinear Configuration..............................................................................................110
F.4.1 Bilinear Switched Capacitor Resistor Equivalent ......................................................110
E.4.2 Twin T with Bilinear Switched Capacitor Resistor Equivalent .................................111
E.4.3 Bootstrapped Twin T with Bilinear Switched Capacitor Resistor Equivalent...........113
APPENDIX F: SPICE NETLIST...........................................................................................117
F.1 OTA ..........................................................................................................................117
F.2 Twin T RC Notch Filter ............................................................................................121
F. 3 Bootstrapped Twin T RC Notch Filter.....................................................................122
F.4 Switched Capacitor Resistor Equivalent ..................................................................123
F.5 Twin T Switched Capacitor Filter.............................................................................125
F.6 Bootstrapped Twin T Switched Capacitor Filter ......................................................128
F.7 OTA and Clock Generator Sub Circuit.....................................................................131
RESEARCH PUBLICATIONS..............................................................................................134
BIOGRAPHY........................................................................................................................135



List of Figures
Figure 1. Typical ECG signal with its corresponding heart motion........................................4
Figure 2. ECG signal acquisition set up. .................................................................................5
Figure 3. ECG signal without the presence of power line interference and ECG signal with
the presence of power line interference. [3] ...............................................................................6
Figure 4. Frequency spectrum of an ECG signal without the presence of power line
interference and an ECG signal with the presence of power line interference. [3]....................6
Figure 5. Unfiltered, corrupted with power line interference ECG signal and its frequency
spectrum. [3]..............................................................................................................................8
Figure 6. Filtered ECG signal and its frequency spectrum. [3]...............................................8
Figure 7. Passive Low Pass Filter Circuit Schematic..............................................................9
Figure 8. Amplitude and Phase Response Curves of a Low Pass Filter. [14] .......................10
Figure 9. SC low pass 50Hz notch biquad. [15]....................................................................10
Figure 10. E-type Fleischer & Laker biquad. [16] ................................................................10
Figure 11. Passive High Pass Filter Circuit Schematic. ........................................................11
Figure 12. Amplitude and Phase Response Curves of a High Pass Filter. [14] ....................11
Figure 13. Passive Band Pass Filter Circuit Schematic.........................................................12
Figure 14. Amplitude and Phase Response Curves of a Band Pass Filter. [14]....................12
Figure 15. 4th Order Bandpass Switched Capacitor Filter. [17] ...........................................12
Figure 16. Biquad bandpass filter. [18] .................................................................................13
Figure 17. Passive Band Reject Filter Circuit Schematic......................................................14
Figure 18. Amplitude and Phase Response Curves of a Band Reject Filter. [14].................14
Figure 19. Q of a Notch Filter. [19].......................................................................................14
Figure 20. 4th Order Notch Filter normally used in the main noise cancellation. [8]............14
Figure 21. Sinusoidal waveform with phase shift ψ. [14] .....................................................15
Figure 22. Phase Response Curves of a All Pass Filter. [14] ................................................15
Figure 23. Elements of a switched-capacitor filter. (a) op amp, (b) capacitor with symbolic
switches, (c) capacitor with MOS switches and (d) a driving clock for the switches. [13] .....16
Figure 24. Symbol for op amp...............................................................................................17
Figure 25. Classical two stage op amp. ....................................................................................18
Figure 26. Folded cascode op amp. ..........................................................................................18
Figure 27. Low voltage switchable op amp. [18] ..................................................................19
Figure 28. Precise OpAmp Gain (POG) realized with a low pass filter. [16] .......................20
Figure 29. Fully differential two switchable output pair opamp. [24] ..................................20
Figure 30. Very low power fully differential switched opamp. [17].....................................21
Figure 31. Operational Amplifier with a Start up, Vbias, current summation, rail to rail input
pair, bias and an output stage. [32]...........................................................................................21
Figure 32. Dynamic CMFB. [24] ..........................................................................................21
Figure 33. CMBF circuit of the fully differential switched op amp. [17] .............................22
Figure 34. Circuit schematic of OTA presented in...................................................................24
Figure 35. Threshold-referenced circuit schematic. .................................................................25
Figure 36. Full OTA circuit schematic.....................................................................................26
Figure 37. OTA chip layout......................................................................................................29
Figure 38. OTA chip micrograph. ............................................................................................29
Figure 39. Chip testing and pin assignments.........................................................................30
Figure 40. Comparator testing configuration 1 and output waveform. ....................................30
Figure 41. Comparator testing configuration 2 and output waveform. ....................................31
Figure 42. Comparator testing configuration 3 and output waveform. ....................................31
Figure 43. Comparator testing configuration 1 and output waveform. ....................................31
Figure 44. CMRR testing configuration and output waveform................................................32
Figure 45. ICMR testing configuration and output waveform. ................................................32
Figure 46. Twin T RC Notch Filter. .........................................................................................33
Figure 47. RC combination versus attenuation graph. .............................................................34
Figure 48. RC combination versus center frequency. ..............................................................34
Figure 49. Twin T RC Notch Filter AC response.....................................................................35
Figure 50. Bootstrapped Twin T RC notch Filter.....................................................................36
Figure 51. Bootstrapped Twin T RC Notch Filter AC Response.............................................36
Figure 52. Voltage divider schematic to test parallel switched capacitor resistor equivalent.
.................................................................................................................................................37
Figure 53. Twin T notch filter with R1 replaced with parallel switched capacitor equivalent.
.................................................................................................................................................38
Figure 54. Bootstrapped Twin T notch filter with R1 replaced with parallel switched capacitor
equivalent.................................................................................................................................38
Figure 55. Twin T and Boostrapped Twin T with Parallel Switched Capacitor AC Response.
.................................................................................................................................................38
Figure 56. Voltage divider schematic to test series switched capacitor resistor equivalent.....39
Figure 57. Twin T notch filter with R1 replaced with series switched capacitor equivalent. ..40
Figure 58. Bootstrapped Twin T notch filter with R1 replaced with series switched capacitor
equivalent.................................................................................................................................40
Figure 59. Twin T and Boostrapped Twin T with Series Switched Capacitor AC Response..40
Figure 60. Voltage divider schematic to test series-parallel switched capacitor resistor
equivalent.................................................................................................................................41
Figure 61. Twin T notch filter with R1 replaced with series-parallel switched capacitor
equivalent.................................................................................................................................41
Figure 62. Bootstrapped Twin T notch filter with R1 replaced with series-parallel switched
capacitor equivalent..................................................................................................................41
Figure 63. Twin T and Boostrapped Twin T with Series-Parallel Switched Capacitor AC
Response..................................................................................................................................42
Figure 64. Voltage divider schematic to test bilinear switched capacitor resistor equivalent..42
Figure 65. Twin T notch filter with R1 replaced with bilinear switched capacitor equivalent.
.................................................................................................................................................42
Figure 66. Bootstrapped Twin T notch filter with R1 replaced with bilinear switched capacitor
equivalent.................................................................................................................................43
Figure 67. Twin T and Boostrapped Twin T with Bilinear Switched Capacitor AC Response.
.................................................................................................................................................43
Figure 68. Twin T with Switched Capacitor AC Response. ....................................................44
Figure 69. Bootstrapped Twin T with Switched Capacitor AC Response. ...........................45
Figure 70. AC Open Loop Gain Pre-Layout Simulation Result...............................................51
Figure 71. Phase Margin Pre-Layout Simulation Result..........................................................52
Figure 72. Slew Rate± and Settling Time Pre-Layout Simulation Result................................53
Figure 73. Rising Edge, Slew Rate+ Pre-Layout Simulation Result........................................54
Figure 74. Falling Edge, Slew Rate- Pre-Layout Simulation Result........................................54
Figure 75. ICMR Pre-Layout Simulation Result......................................................................55
Figure 76. CMRR Pre-Layout Simulation Result. ...................................................................56
Figure 77. PSRR+ Pre-Layout Simulation Result....................................................................57
Figure 78. PSRR- Pre-Layout Simulation Result.....................................................................57
Figure 79. Output Swing Pre-Layout Simulation Result..........................................................58
Figure 80. Input Offset Voltage Pre-Layout Simulation Result...............................................59
Figure 81. Temperature Variation Pre-Layout Simulation Result. ..........................................60
Figure 82. AC Open Loop Gain Pre-Layout Simulation Result...............................................61
Figure 83. Phase Margin Pre-Layout Simulation Result..........................................................62
Figure 84. Slew Rate± and Slew Rate Pre-Layout Simulation Result. ....................................63
Figure 85. Rising Edge, Slew Rate Pre-Layout Simulation Result. .........................................64
Figure 86. Falling Edge, Slew Rate Pre-Layout Simulation Result. ........................................64
Figure 87. ICMR Pre-Layout Simulation Result......................................................................65
Figure 88. CMRR Pre-Layout Simulation Result. ...................................................................66
Figure 89. PSRR+ Pre-Layout Simulation Result....................................................................67
Figure 90. PSRR- Pre-Layout Simulation Result.....................................................................67
Figure 91. Output Swing Pre-Layout Simulation Result..........................................................68
Figure 92. Input Offset Voltage Pre-Layout Simulation Result...............................................69
Figure 93. Temperature Variation Pre-Layout Simulation Result. ..........................................70
Figure 94. AC Open Loop Gain Post-Layout Simulation Result. ............................................71
Figure 95. Phase Margin Post-Layout Simulation Result. .......................................................72
Figure 96. Slew Rate± and Settling Time Post-Layout Simulation Result. .............................73
Figure 97. Slew Rate+ Post-Layout Simulation Result............................................................74
Figure 98. Slew Rate- Post-Layout Simulation Result.............................................................74
Figure 99. ICMR Post-Layout Simulation Result. ...................................................................75
Figure 100. CMRR Post-Layout Simulation Result.................................................................76
Figure 101. PSRR+ Post-Layout Simulation Result. ...............................................................77
Figure 102. PSRR- Post-Layout Simulation Result. ................................................................77
Figure 103. Output Swing Post-Layout Simulation Result. .....................................................78
Figure 104. Input Offset Voltage Post-Layout Simulation Result. ..........................................79
Figure 105. Temperature Variation Post-Layout Simulation Result........................................80
Figure 106. Schematic for Parallel Switched Capacitor Resistor Equivalent. .........................91
Figure 107. 564MΩ Parallel Switched Capacitor Resistor Equivalent. ...................................91
Figure 108. 282MΩ Parallel Switched Capacitor Resistor Equivalent. ...................................91
Figure 109. Twin T Schematic with Parallel Switched Capacitor. ..........................................92
Figure 110. Twin T output at 500Hz input signal. ...................................................................92
Figure 111. Twin T output at 150Hz input signal. ...................................................................92
Figure 112. Twin T output at 120Hz input signal. ...................................................................93
Figure 113. Twin T output at 90Hz input signal. .....................................................................93
Figure 114. Twin T output at 60Hz input signal. .....................................................................93
Figure 115. Twin T output at 30Hz input signal. .....................................................................94
Figure 116. Twin T output at 1Hz input signal. .......................................................................94
Figure 117. Bootstrapped Twin T Schematic with Parallel Switched Capacitor. ....................94
Figure 118. Bootstrapped Twin T output at 500Hz input signal. .............................................95
Figure 119. Bootstrapped Twin T output at 150Hz input signal. .............................................95
Figure 120. Bootstrapped Twin T output at 120Hz input signal. .............................................95
Figure 121. Bootstrapped Twin T output at 90Hz input signal. ...............................................96
Figure 122. Bootstrapped Twin T output at 60Hz input signal. ...............................................96
Figure 123. Bootstrapped Twin T output at 30Hz input signal. ...............................................96
Figure 124. Bootstrapped Twin T output at 1Hz input signal. .................................................97
Figure 125. Schematic for Series Switched Capacitor Resistor Equivalent.............................97
Figure 126. 564MΩ Series Switched Capacitor Resistor Equivalent. .....................................97
Figure 127. 282MΩ Series Switched Capacitor Resistor Equivalent. .....................................98
Figure 128. Twin T Schematic with Series Switched Capacitor..............................................98
Figure 129. Twin T output at 500Hz input signal. ...................................................................98
Figure 130. Twin T output at 150Hz input signal. ...................................................................99
Figure 131. Twin T output at 120Hz input signal. ...................................................................99
Figure 132. Twin T output at 90Hz input signal. .....................................................................99
Figure 133. Twin T output at 60Hz input signal. ...................................................................100
Figure 134. Twin T output at 30Hz input signal. ...................................................................100
Figure 135. Twin T output at 1Hz input signal. .....................................................................100
Figure 136. Bootstrapped Twin T Schematic with Series Switched Capacitor......................101
Figure 137. Bootstrapped Twin T output at 500Hz input signal. ...........................................101
Figure 138. Bootstrapped Twin T output at 150Hz input signal. ...........................................101
Figure 139. Bootstrapped Twin T output at 120Hz input signal. ...........................................102
Figure 140. Bootstrapped Twin T output at 90Hz input signal. .............................................102
Figure 141. Bootstrapped Twin T output at 60Hz input signal. .............................................102
Figure 142. Bootstrapped Twin T output at 30Hz input signal. .............................................103
Figure 143. Bootstrapped Twin T output at 1Hz input signal. ...............................................103
Figure 144. Schematic for Series-Parallel Switched Capacitor Resistor Equivalent. ............103
Figure 145. 564MΩ Series-Parallel Switched Capacitor Resistor Equivalent.......................104
Figure 146. 282MΩ Series-Parallel Switched Capacitor Resistor Equivalent.......................104
Figure 147. Twin T Schematic with Series-Parallel Switched Capacitor. .............................104
Figure 148. Twin T output at 500Hz input signal. .................................................................105
Figure 149. Twin T output at 150Hz input signal. .................................................................105
Figure 150. Twin T output at 120Hz input signal. .................................................................105
Figure 151. Twin T output at 90Hz input signal. ...................................................................106
Figure 152. Twin T output at 60Hz input signal. ...................................................................106
Figure 153. Twin T output at 30Hz input signal. ...................................................................106
Figure 154. Twin T output at 1Hz input signal. .....................................................................107
Figure 155. Bootstrapped Twin T Schematic with Series-Parallel Switched Capacitor. .......107
Figure 156. Bootstrapped Twin T output at 500Hz input signal. ...........................................107
Figure 157. Bootstrapped Twin T output at 150Hz input signal. ...........................................108
Figure 158. Bootstrapped Twin T output at 120Hz input signal. ...........................................108
Figure 159. Bootstrapped Twin T output at 90Hz input signal. .............................................108
Figure 160. Bootstrapped Twin T output at 60Hz input signal. .............................................109
Figure 161. Bootstrapped Twin T output at 30Hz input signal. .............................................109
Figure 162. Bootstrapped Twin T output at 1Hz input signal. ...............................................109
Figure 163. Schematic for Bilinear Switched Capacitor Resistor Equivalent........................110
Figure 164. 564MΩ Bilinear Switched Capacitor Resistor Equivalent. ................................110
Figure 165. 282MΩ Bilinear Switched Capacitor Resistor Equivalent. ................................110
Figure 166. Twin T Schematic with Bilinear Switched Capacitor.........................................111
Figure 167. Twin T output at 500Hz input signal. .................................................................111
Figure 168. Twin T output at 150Hz input signal. .................................................................111
Figure 169. Twin T output at 120Hz input signal. .................................................................112
Figure 170. Twin T output at 90Hz input signal. ...................................................................112
Figure 171. Twin T output at 60Hz input signal. ...................................................................112
Figure 172. Twin T output at 30Hz input signal. ...................................................................113
Figure 173. Twin T output at 1Hz input signal. .....................................................................113
Figure 174. Bootstrapped Twin T Schematic with Bilinear Switched Capacitor. .................113
Figure 175. Bootstrapped Twin T output at 500Hz input signal. ...........................................114
Figure 176. Bootstrapped Twin T output at 150Hz input signal. ...........................................114
Figure 177. Bootstrapped Twin T output at 120Hz input signal. ...........................................114
Figure 178. Bootstrapped Twin T output at 90Hz input signal. .............................................115
Figure 179. Bootstrapped Twin T output at 60Hz input signal. .............................................115
Figure 180. Bootstrapped Twin T output at 30Hz input signal. .............................................115
Figure 181. Bootstrapped Twin T output at 1Hz input signal. ...............................................116

[1] J. C. Huhta and J. G. Webster, “60-Hz Interference in Electrocardiography”, IEEE Transactions on Biomedical Engineering, vol. BME-20, no. 2, pp. 91-101, March 1973.
[2] M. S. Chavan, R. A. Agarwala and M. D. Ulpane, “Design and implementation of Digital FIR Equiripple Notch Filter on ECG Signal for removal of Power line Interference”, WSEAS Transactions on Signal Processing, issue 4, vol. 4, pp221-230, April 2008.
[3] S. Witthayapradit, S Chitwong and S. Tumthong, “Tracking Notch Filter For Electrocardiograph measurement”, IEEE CCECE/CCGEI, pp. 1395-1398, May 2006.
[4] K. N. Kadhim, S. M. R. Taha and W. A. Mahmoud, “A New Method For Filtering and Segmentation of ECG Signal”, IEEE Engineering in Medicine and Biology Society 10th Annual International Conference, 1998.
[5] P. S. Hamilton, “60Hz Filtering for ECG Signals To Adapt or Not to Adapt”, IEEE, pp. 779-780, 1993.
[6] S. C. Pei and C. C. Tseng, “Elimination of AC Interference in ECG Using IIR NF with Transient Suppression”, IEEE Transactions on Biomedical Engineering, vol. 42, no. 11, pp. 1128-1132, November 1995.
[7] L. Hejjel and L. Kellenyi, “The corner frequencies of the ECG amplifier for heart rate variability analysis”, Physiological Measurement, 26 39-47, 2005.
[8] R. Ramos, A. Manuel-Lazaro, J. Del Rio and G. Olivar, “FPGA-Based Implementation of an Adaptive Canceller for 50-60Hz Interference in ECG”, IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 6, pp. 2633-2640, December 2007.
[9] R. Gregorian, “Switched-Capacitor Filter Design Using Cascaded Sections”, IEEE Transactions on Circuits and Systems, vol. CAS-27, no. 6, pp.515-521, June 1980.
[10] D. R. Frey and L. Steigerwald, “An Adaptive Analog Notch Filter Using Log Filtering”, IEEE, pp. 297-300, 1996.
[11] B. K. Casper, D. J. Comer and D. T. Comer, “An Integrable 60-Hz Notch Filter”, IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, vol. 46, no.1, pp.74-77, January 1999.
[12] L. Hajjel, “Suppression of PLI by Analog Notch Filtering in the ECG signal for
131
HRV Analysis - to do or not to do”, Med Sci Monit, 10(1):MT6-13, 2004.
[13] H. Baher, “Microelectronic Switched Capacitor Filters”, IEEE Circuits and Devices, pp. 33-36, January 1991.
[14] National Semiconductor, “A Basic Introduction to Filters – Active, Passive and Switched-Capacitor”, Application Note 779, April 1991.
[15] Q. Huang and M. Oberle, “A 0.5-mW Passive Telemetry IC for Biomedical Applications”, IEEE journal of Solid-State Circuits, vol. 33, no. 7, pp. 937-946, July 1998.
[16] A. Bischirotto, F. Severi and R. Castello, “A 200-Ms/s 10mW Switched-Capacitor Filter in 0.5um CMOS Technology, IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1215-1219, August 2000.
[17] J. S. Chiang, H. P. Chen and C. M. Ying, “A 1V 0.54uW Fourth Order Switched Capacitor Filter with Switched Opamp Technique for Cardiac Pace Maker Sensing Channel”, IEEE ISCAS, 2003.
[18] A. Baschirotto and R. Castello, “A i-V 1.8-MHz CMOS Switched-Opamp SC Filter with Rail-to-Rail Output Swing”, IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp.1979-1986, December 1997.
[19] B. Carter, “High-speed notch filters”, Texas Instruments, Analog Applications Journal, 2006.
[20] G. M. Jacobs, D. J. Allstot, R. W. Brodersen and P. R. Gray, “Design Techniques for MOS Switched Capacitor Ladder Filters”, IEEE Transactions on Circuits and Systems, vol. cas-25, no. 12, pp. 1014-1021, December 1978.
[21] H. P. Ninh, T. Moue, T. Kurashina, K. Okada and A. Matsuzawa, “A CMOS Direct Sampling Mixer Using Switched Capacitor Filter Technique for Software-Defined Radio”, IEEE, pp. 103-104, 2008.
[22] H. Shafeeu, A. Betts and J. Taylor, “A Continuously Variable Tuning Techinique for Switched Capacitor Filters”, IEEE Transactions on Circuits and Systems – I: Fundamental Theory and Applications, vol. 43, no. 9, pp.798-800, September 1996.
[23] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design, 2nd ed.”, New York: Oxford University Press, 2002.
[24] V. S. L. Cheung, H. C. Luong and W. H. Ki, “A 1-V CMOS Switched-Opamp Switched-Capacitor Psedu-2-Patch Filter”, IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 14-22, January 2001.
[25] C. M. Chang, C. L. Hou, W. Y. Chung, J. W. Horng, and C. K. Tu, “Analytical
132
Synthesis of High-Order Single-Ended-Input OTA-Grounded C All-Pass and Band-Reject Filter Structures”, IEEE Transactions on Circuits and Systems – I : Regular Papers, vol. 53, no. 3, pp. 489-498, March 2006.
[26] A. C. B. Albason, et. al., “Design Methodologies for Low-Power CMOS Operational Amplifiers in 0.25um Digital CMOS Process”, IEEE, 2006.
[27] J. G. Webster, “Medical Instrumentation: Application and Design, 3rd ed.”, New York: John Wiley & Sons, 1998.
[28] K. Su, “Analog Filters, 2nd ed.”, Kluwer Academic Publisher, 2002.
[29] S. A. Pactitis, “Acitve Filters Theory and Design”, New York: CRC Press, 2008.
[30] S. Winder, “Analog and Digital Filter Design, 2nd ed.”, Newnes, 2002.
[31] C. M. Chang, C. L. Hou, W. Y. Chung, J. W. Horng and C. K. Tu, “Analytical Synthesis of High-Order Single Ended-Input OTA-Grounded C All-Pass and Band Reject Filter Structures”, IEEE Transactions on Circuits and Systems, vol. 53, no. 3, pp. 489-498, March 2006.
[32] Shang-Yi You, “Design and Implementation of Front-End Readout Chip for Electrocardiac Signal Acquisition Systems”, Chung Yuan Christian University Master Degree Thesis, Taiwan, January 2009.
[33] R. Schaumann and M. E. V. Valkenburg, “Design of Analog Filters”, New York: Oxford University Press, 2001.
[34] K. R. Laker and W. M. C. Sasen, “Design of Analog Integrated Circuits and Systems”, New York: McGraw-Hill, Inc., 1994.