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研究生:程駿華
研究生(外文):Chun-Hua Cheng
論文名稱:高速度低功率非零時序差異電路之資源繫結問題研究
論文名稱(外文):Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
指導教授:黃世旭黃世旭引用關係
指導教授(外文):Shih-Hsu Huang
學位類別:博士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:85
中文關鍵詞:時序差異最佳化高階合成資源繫結電源閘
外文關鍵詞:High-Level SynthesisClock Skew OptimizationPower GatingResource
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高速度與低功率對於邊緣觸發電路設計,為兩個重要的設計目標。對高速度與低功率的電路,時序差異已廣為人知可被利用來當作可控管的資源。就我們所知,過去尚未有人在高階合成階段,考慮如何利用時序差異來最佳化電路。在此篇論文中,我們先是同時應用時鐘排序與暫存器繫結最小化我們的時鐘週期;接著同時應用時鐘排序、電源閘電路選擇與資源器繫結最小化我們的待機漏電流。測試電路結果顯示,我們的方法可以達到非常好的效果。
High speed and low power are two important objectives in the design of edge-triggered circuits. It is well known that the clock skew can be utilized as a manageable resource for high speed and low power. To the best of our knowledge, the circuit is never optimized for utilizing the clock skew in the high-level synthesis stage. In this dissertation, we study resource binding of high-speed low-power nonzero clock skew circuits. First, we study the simultaneous application of clock scheduling and register binding for clock period minimization. Then, we study the simultaneous application of clock scheduling, power gating implementation selection, and resource binding for standby leakage current minimization. Finally, benchmark data consistently show that our approaches achieve very good results.
[Contents]
摘要..................................................................I
Abstract..................................................................II
Acknowledgements......................................................III
Contents..............................................................IV
List of Figures.......................................................V
List of Tables........................................................VI

Chapter 1. Introduction...............................................1
Chapter 2. Preliminaries..............................................5
2.1 High Level Synthesis..............................................6
2.2 Register Binding..................................................7
2.3 Functional Unit Binding...........................................9
2.4 Circuit Graph.....................................................9
2.5 Minimum-Period Clock Scheduling...................................12
Chapter 3. Register Binding for Minimizing Clock Period...............14
3.1 Motivation........................................................15
3.2 MILP Formulation..................................................18
3.3 The Proposed Heuristic Approach...................................24
Chapter 4. Resource Binding for Minimizing Standby Leakage Current....37
4.1 Functional Unit Library with Power Gating Considered..............38
4.2 Drawback of Existing Flow.........................................40
4.3 MILP Formulation..................................................46
4.4 The Proposed Heuristic Approach...................................53
Chapter 5. Experimental Results and Comparisons.......................59
5.1 Result of Minimum Clock Period Register Binding...................60
5.2 Result of Minimum Standby Leakage Current Resource Binding........67
Chapter 6 Concluding Remarks and Future Works.........................70
References............................................................71

[List of Figures]
Figure 1.1
(a) Functional unit with power gating
(b) Sleep transistor is modeled as a resistor in active mode..........3
Figure 2.1
(a) Scheduled DFG ex1
(b) Lifetime analysis.................................................8
Figure 2.2
(a) Circuit graph G1
(b) Constraint graph Gcg(G1)..........................................11
Figure 3.1
(a) Circuit graph G2
(b) Constraint graph Gcg(G2)..........................................17
Figure 3.2
(a) Circuit graph G3
(b) Constraint graph Gcg(G3)..........................................18
Figure 3.3 Pseudo code of our heuristic approach......................27
Figure 3.4 Snapshots of our heuristic algorithm I.....................31
Figure 3.5 Snapshots of our heuristic algorithm II....................36
Figure 4.1 Scheduled DFG ex2..........................................41
Figure 4.2
(a) Circuit graph G4
(b) Constraint graph Gcg(G4)..........................................43
Figure 4.3
(a) Circuit graph G5
(b) Constraint graph Gcg(G5)..........................................46
Figure 4.4 Our heuristic approach.....................................53

[List of Tables]
Table 4.1. Delay-leakage characterization of multiplier and adder.....40
Table 5.1. Characteristics of benchmark circuits......................62
Table 5.2. Our experimental results...................................65
Table 5.3. The overheads of our heuristic approach on the number of registers
(for working with the lower bound of the clock period) ...............66
Table 5.4. Clock period reductions of our approach
(under the constraint that the lower bound of the number of registers is used)
over the left edge algorithm..........................................67
Table 5.5. Functional unit library used in our experiments............68
Table 5.6. Description of benchmark circuits..........................68
Table 5.7. Experimental results and comparisons.......................69
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