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研究生:卜珮翠
研究生(外文):Petry Purenia
論文名稱:Sketch演算法於網路應用之快取記憶體架構效能分析
論文名稱(外文):The Performance Analysis of Cache Memory Organization for Sketch-based Network Applications
指導教授:賴裕昆鍾文耀鍾文耀引用關係
指導教授(外文):Yu-Kuen LaiWen-Yaw Chung
學位類別:碩士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:52
中文關鍵詞:快取記憶體網路處理器sketchsimplescalar
外文關鍵詞:cache memorynetwork processorsketchsimplescalar
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由於Sketch演算法有著能將川流的網路資料總結成一組簡潔資料的特性,它引起了許多網路研究者莫大的注意。近來,以Sketch為主的應用也出現於不同的領域之中,而我們的研究便是是以SimpleScalar進行以不同快取記憶體配置使用於Sketch網路應用程式之模擬,並觀察網路處理器上的快取記憶體在處理以網路流為主的封包時所呈現的效能。經由實驗的結果,我們可以發現網路封包流在空間上有一定程度的暫存性。也由於Sketch資料結構擁有著隨機分布的特性,它相對適合於多組數的集合關聯式的記憶體架構,而每個組所取用的資料數則越少越好,並採用最近最少被採用(least‐recently‐used)的資料替換原則。
Sketch data structures gain much attention from researchers in networking community. It can be used to build compact summaries on the streaming data of network traffic. Currently, many applications use sketch method applied in many fields. This research, explore various cache memory configurations for a sketch-based application on SimpleScalar simulator. The goal is to observe the effectiveness of cache memory on network processor for flow-based packet processing. The experiment results demonstrate sufficient amount of temporal locality in the network traffic traces. Due to the randomized property for sketch data structure, it favors the architecture of higher degree of associativity, small line size and least-recently-used replacement policy.
目錄

摘要 i
Abstract ii
Acknowledgement iii
目錄 iv
表目錄 vii
Chapter 1 1
1.1 Introduction 1
1.2 Current Research Status 2
1.3 Objective of The Research 4
1.4 Scope and Limitation 5
Chapter 2 6
2.1 Network Processor 6
2.2 Cache Memory 8
2.3 Sketch 10
2.3.1 Count-Min Sketch 10
2.3.2 K-ary Sketch 12
2.4 SimpleScalar 14
2.5 Sim-Outorder 16
Chapter 3 19
3.1 Equipments 19
3.2 Cache Memory Configurations 19
3.3 Sketch Application 20
3.4 Trace Files 20
3.5 Accuracy 22
Chapter 4 25
4.1 Execution Cycle 25
4.2 Cache Line Size 29
4.3 Set Associativity 31
4.4 Replacement Policy 33
4.5 Cache Size 35
Chapter 5 39
References 40

圖目錄

Figure 1. Example of a Cache-Based Memory System 8
Figure 2. Multiple Levels of Cache Memory 9
Figure 3. Sketch-based change detection [12] 13
Figure 4. Process of Simulation in SimpleScalar simulator 14
Figure 5. SimpleScalar Models 15
Figure 6. Four-Way Set Associative Cache [45] 18
Figure 7. Flow throughput of trace files 21
Figure 8. Total number of distinct source IP in trace files 21
Figure 9. Total number of packets in trace files 22
Figure 10. Execution time vs. cache size for ODU trace 26
Figure 11. Execution time vs. cache size for ODU trace 27
Figure 12. Execution time vs. cache size for ODU trace 28
Figure 13. Execution time vs. cache size for ODU trace 28
Figure 14. Data cache miss rate with various cache line size. 30
Figure 15. Data cache miss rate with various cache line size. 31
Figure 16. Data cache miss rate with various set associative. 32
Figure 17. Data cache miss rate vs. replacement policy on 32 KB cache size, 32 bytes line size, 2-way set associative 34
Figure 18. Data cache miss rate vs. replacement policy on 32 KB cache size, 32 bytes line size, 32-way set associative 35
Figure 19. Data cache miss rate vs. replacement policy on 16 KB cache size, 16 bytes line size, 2-way set associative 35
Figure 20. Data cache miss rate for MEM trace 36
Figure 21. Data cache miss rate for ODU trace 37
Figure 22. Data cache miss rate for AMP trace 37
Figure 23. Data cache miss rate for PSC trace 38

表目錄

Table 1. Cache memory configurations for some of f-the-self network processors 19
Table 2. Result of Count-Min sketch point query estimation for AMP trace 23
Table 3. Result of Count-Min sketch point query estimation for MEM trace 23
Table 4. Result of Count-Min sketch point query estimation for ODU trace 23
Table 5. Result of Count-Min sketch point query estimation for PSC trace 24
Table 6. Data cache miss rate (%) with various cache line size on Cache size (KB) 29
Table 7. Data cache miss rate (%) with various set associative on cache line size 30
Table 8. Data cache miss rate (%) with various set associative on Cache Size (KB) 32
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