臺灣博碩士論文加值系統

近來來隨著半導體製程的精進與微縮，能儲存多記憶位元於單一
元件內的新型非揮發性記憶體發展，逐漸地受到注目與重視。而相較
於以往利用浮動閘極儲存記憶元的非揮發性記憶體，新型的非揮發性
記憶體更強調在製程上簡化以降低製造成本，因此如何利用現行的標
準邏輯製程開發出新型的多記憶元非揮發性記憶體，為現今各方所努
力的方向與目標。
此論文研究之主題即為一新型嵌入性非揮發記憶體(NOI)，除具
有與現行邏輯製程相容之特性，更具有在單一元件內儲存雙位元的優
點。相較於SONOS 是利用閘極介電質中的氮化矽來儲存電荷，NOI 則
是利用氮化矽側壁 (SiN4 Sidewall)來儲存電荷，因此可以解決
SONOS 在元件微縮時所產生的位元合併(Bit-Merging)的問題。
此論文乃首次利用Charge Pumping (CP)來研究電荷於NOI 氮化
矽側壁中的分佈情況，並輔以電腦模擬軟體TSUPREM4 和MEIDI 來佐
證此電荷分佈狀況。從實驗與模擬結果可得知，利用通道熱電子所注
入的電子，在臨界電壓漂移 0.8 伏特(△Vth=0.8V)時, 儲存電荷的
分佈範圍大小約為90nm，且其最大儲存電荷密度的位置乃是靠近汲
極邊界。

Recently, the discrete charge trapping non-volatile memory (NVM) devices
received much attention due to their potential multi-bit storage in a unit cell. In
contrast to those floating gates memories, oxide-nitride-oxide (ONO) charge
trapping structures are explored to store charges in NROM and TwinMONOS
for high density NVM devices. Newly developed gate-to-drain non-overlapped
implantation (NOI) MOSFETs are proposed by using the silicon nitride (SiN)
spacers as charge trapping media. NOI are fully compatible with existing
industrial CMOS fabrications without adding process modification and mask
tooling cost. Channel hot electron injection (CHEI) and band-to-band hot hole
enhanced injection (HHEI) are used to program and erase the NOI device for
NVM operations.
Novel gate-to-drain non-overlapped implantation (NOI) nMOSFETs have
been developed as potential multi-bit-per-cell non-volatile memory (NVM)
devices. The lateral charge distribution of the NOI NVM device programmed by
channel hot electron injection (CHEI) is investigated by charge pumping (CP)
techniques with presumed interface trap distributions. For the first time, the CP
results have revealed the lateral charge distribution and trapping density at the
NOI’s programmed state (ΔVth=0.8V). The maximum trapping charge density
locates near its drain junction. The charge distribution is estimated about 90nm
in length and spread widely over the NOI region. 2-D simulators with charge
bars using the same charge trapping distribution confirm the experimental
results by fitting their IDS-VG curves.

中文摘要 I
Abstract II
Acknowledgments III
Contents IV
Figure Captions VII
Table Captions…………………………….…………………………XIII
第一章 非揮發性記憶元件之回顧與介紹 IX
第二章 NOI非揮發性記憶體之電性操作與原理 X
第三章 電荷幫浦於NOI記憶體元件之應用 XI
第四章 電荷分佈之電腦模擬驗證 XII
Chapter1 Introduction to Non-Volatile Memory Devices 1
1-1 Role of Non-Volatile Memory Devices in Microelectronic systems …………………………………………1
1-2 Evolution of NVM Devices 3
1-3 Floating Gate Memory Devices 12
1-3.1 Stacked Gate Memory Devices 12
1-3.2 Split-Gate Memory Devices 13
1-4 Charge-Trapping Memory Devices 16
1-4.1 Metal-Nitride-Oxide-Silicon (MNOS) 17
1-4.2 Metal Oxide Nitride Oxide Silicon (MONOS) and Poly-Silicon Oxide Nitride Silicon (SONOS) 18
1-4.3 NROM 19
1-4.4 Twin-MONOS 20
1-5 NVM Devices Development Trends 21
Chapter2 Electrical Operations and Principles of NOI Memory Devices 23
2-1 NOI Cell Structure and Brief Fabrication Flow 24
2-2 The Band-to-Band Tunneling Effect (BTBT) 28
2-3 Hot Carrier Injection 32
2-3-1 Substrate Hot-Electron (SHE) Injection 33
2-3-2 Channel Hot Electron Injection (CHEI) 35
2-3-3 Channel Initiated Secondary Electron (CHISEL) Injection 38
2-3-4 Drain Avalanche Hot Carrier (DAHC) Injection 40
2-3-5 The BTBT Induced Hot Carrier Injection (BBHC) ……………………………………………………….41
2-4 Charge Transportation in Silicon Nitride 43
2-5 NOI Memory Device Operation 44
2-5.1 Program 45
2-5.2 Erase 46
2-5.3 Read 47
2-5.3.1 Forward Read 49
2-5.3.2 Reverse Read 50
Chapter3 Charge Pumping Techniques and Application on NOI Memory Device 52
3-1 Nonvolatile Memory Reliability Concerns 52
3-2 Charge Pumping Techniques 53
3-3 Charge Pumping Experiments 59
3-3.1 Experimental Setup 60
3-3.2 Experimental Procedures 61
3-4 Charge Profiling and Discussion 65
Chapter4 Simulation for Charge Profiling Verification 78
4-1 Process simulation: Doping profile and device X-section ……………………………………………………………..78
4-2 Device Simulation: Verification of charge profiling 79
4-3 Results and Discussion 81
4-4 Program Efficiency Evaluation by TCAD simulation 82
4-5 Conclusion 87
Reference ……………………………………………………………..90

Figure Captions

Figure 1-1. Worldwide Non-volatile and Total Memory Markets, 2002-2010. (Source: BBC, Inc.)…………………………1
Figure 1-2. Types of Semiconductor Memory ………………………4
Figure 1-3. History of Non-Volatile Memories ……………………...4
Figure 1-4. Two classes of nonvolatile semiconductor memory devices: (a) Floating gate devices; (b) Charge-trapping devices (MIOS device)…………………………………...7
Figure 1-5. Current-voltage characteristic of a memory device in the erased and programmed state, showing the Vt shift and the memory window. (a) Charge trapped in floating gate. (b) Threshold voltage shifted when the charges are trapped in floating gate.…………………………………9
Figure 1-6. (a) EPROM Programming (b) EEPROM Erasing mechanism for stacked gate memory devices…………11
Figure 1-7. The cross section of the split gate memory device. (a) Cross Section of Split Gate device Structure, (b) Program: Channel Hot Electron Injection and (c) Erase: FN Tunneling. …………………………………………..16
Figure 1-8. Structure of charge-trapping device. High deep-level trap density dielectrics such as Si3N4 or Al2O3 are used to trap charges. …………………………………………17
Figure 1-9. Schematic cross section of SONOS……………………18
Figure 1-10. (a) Cell array layout of NROM. (b) Cross section of NROM along a word line. The electron storage regions are indicated by arrows, and will be referred to as Bit-1 and Bit-2. ……………………………………………….19
Figure 1-11. Schematic cross section of twin-MONOS. ……………21
Figure 2-1. NOI Memory device brief fabrication flow…………..25.
Figure 2-2. (a) Band diagram of Thermal Equilibrium (b) Band diagram of Band-to-Band tunneling or Zener breakdown. ……………………………………………..29
Figure 2-3. Scheme of BTBT mechanism. …………………………31
Figure 2-4. Band diagram of band-to-band tunneling across the oxide. ……………………………………………………32
Figure 2-5. (a) Schematic and (b) energy band diagram of the substrate hot electrons injection. ……………………..34
Figure 2-6. The lateral electric field in the channel shows that the highest electric field is near the drain junction. ……..36
Figure 2-7. (a) Schematic description of the lucky electron model. (b) Energy band diagram of channel hot electron injection. ………………………………………………..37
Figure 2-8. (a) CHE program operation (Vb=0). (b) CHISEL program operation (Vb<0). (c) Energy band diagram of CHE and CHISEL. …………………………………….39
Figure 2-9. Gate current versus gate voltage for n-MOS at a constant high drain bias. ………………………………40
Figure 2-10. The high VD reverse the vertical field is found at 0<VG<VD. ……………………………………………….41
Figure 2-11. The schematic of BBHC in (a) n-MOSFET and (b) p-MOSFET. …………………………………………….41
Figure 2-12. Charge transportation mechanisms in silicon nitride. (a) Poole-Frenkel conduction and (b) hopping conductance.. …………………………………………...44
Figure 2-13. The schematic of NOI device programming by Channel hot electron injection. ………………………………….46
Figure 2-14. The schematic of NOI device Erasing by BTBT Hot hole injection. …………………………………………..47
Figure 2-15. Two-bit operation for NOI Memory device. …………48
Figure 2-16. Forward Read Mechanism. …………………………...50
Figure 2-17. Reverse Read Mechanism. …………………………….51
Figure 3-1. Overview of charge pumping measurements: (a) Pulse waveform for base voltage sweep; pulse amplitude is constant. (b) Pulse waveform for amplitude sweep; base voltage is constant. …………………………………….55
Figure 3-2. Circuit diagram and energy bands for charge pumping measurements. …………………………………………56
Figure 3-3. NOI Structure and Dimension. ……………………….59
Figure 3-4. Basic experimental system setup for charge pumping.61
Figure 3-5. Initial/programmed charge pumping current collected at drain side. ……………………………………………64
Figure 3-6. Initial/programmed charge pumping current collected at source side. …………………………………………..65
Figure 3-7. Type (a): Initial State Nit(x) distribution (Uniform), Type (b): InitialProgrammed State Nit(x) (Uniform), Type (c): Programmed State Nit(x) (Non-uniform).NOI device. ………………………………………………….67
Figure 3-8. (a) Formation of transfer curve by integrating type-b Nit(x) assumption. (b) Initial/Program state transfer curves for type-b Nit(x) assumption. …………………68
Figure 3-9. Transferring scheme from Icp(Vh) to local threshold voltage Vth (x). …………………………………………69
Figure 3-10. (a) Formation of transfer curve by integrating type-b Nit(x) assumption. (b) Initial/Program state transfer curves for type-b Nit(x) assumption. ………………….70
Figure 3-11. Combining the Vth(x)_D and Vth(x)_S and ruling out the far-end inaccuracy to complete the initial/programmed local threshold voltage Vth(x) in the NOI device. …….72
Figure 3-12. Fringing capacitance ΔCfr corresponds to each distance x in the SiN spacer. ………………………………….…74
Figure 3-13. Local threshold voltage Vth(x) for Nit assumption of three types along the lateral position in a programmed NOI device. Vth(x) mismatch between type-a, type-b, and type-c Nit(x) is Δxa-b = 22nm and Δxa-b = 5nm, respectively. …………………………………………….75
Figure 3-14. Local threshold voltage Vth(x) of the programmed and initial states for obtaining the ΔVth(x). The maximum Vth(x) located near the drain junction. ……………….76
Figure 3-15. The nitride trapped charge distribution with relative positions of NOI MOSFETs. Nnt(x) peaks near the drain junction edge. …………………………………………..77
Figure 4-1. Simulated doping profile underneath the SiN spacer in NOI device with 125 nm spacer length. ………………78
Figure 4-2. The nitride trapped charge distribution with relative positions of NOI MOSFETs. Nnt(x) peaks near the drain junction edge. …………………………………………..79
Figure 4-3. Program state negative charges in spacer nitride node in Drain side. …………………………………………...80
Figure 4-4. The IDS - VG comparison of simulated and experimental results. …………………………………………………..81
Figure 4-5. Maximum programmed oxide fields above the NOI and the central channels of the simulated NOI devices are compared among different VG and VD. The maximum oxide field increases as VG increases and declines as VD increases. ……………………………………………….83
Figure 4-6. Channel potential distributions of NOI devices having different SiN spacer length are simulated under programming condition. The potential distribution is divided into three segments, corresponding to two NOI channels under SiN spacer and the central channel region under the polygate. …………………………….84
Figure 4-7. Oxide field distributions of NOI devices having different SiN spacer length are simulated under programming condition. The maximum oxide field to program the new NOI device reaches only about 6.25MV/cm in the central channel region. …………...85
Figure 4-8. Lateral channel field distribution under a SiN spacer with different SiN spacer length are simulated under specified programming conditions. Compared to the NOI devices with 65nm and 80nm SiN spacers, the NOI device with 125nm SiN spacer shows the decreased maximum lateral electric field near its drain junction………………………………………………….86

Table Captions

Table 1-1. The Trapping Mechanisms of Memory products. …..11
Table 2-1. Resultant mechanisms relate to different carrier energies. ………………………………………………..36
Table 2-2. Operation conditions of the NOI Device as an NVM. …………………………………………………...49
Table 3-1. Operation of charge pumping conditions of the NOI Device as an NVM. …………………………………….60

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