隨著積體電路元件（Integrated Circuit；IC）之技術節點進入100 nm世代後，阻障層之厚度要求將隨之而變得更加嚴謹，而傳統使用PVD或CVD之製備方法因其階梯覆蓋性（Step Coverge）不良與順依性（Confirmity）不佳，因此其製備之Ta/TaN阻障層將無法滿足次奈米世代之要求，因此開發新的製程技術與新穎替代材料系統是被多方期待。而在半導體工業藍圖中，原子層沉積（Atomic Layer Deposition；ALD）與電化學沉積（Electrochemical Plating；ECP）被視為兩個值得重視的製程技術替代方案。
本研究使用電化學之無電鍍製成沉積薄膜，並採用專利性之超微密鎳顆粒做為催化晶種層。分別探討10 nm之Co-P阻障層對於銅薄膜在高溫熱處理下之行為與錳原子的摻雜對於銅薄膜之高溫熱處理下之行為，並利用掃描式電子顯微鏡（Scanning Electron Microscopy；SEM）及X光繞射儀（X-ray Diffractometer；XRD）分析薄膜之表面型態與薄膜組織；歐傑電子分析儀（Auger Electron Spectrometer；AES）及電壓-電流特性量測系統（I-V Measurement System）分析其是否具有抑制銅原子在高溫熱處理下之擴散行為；並且使用四點探針（Four-point Probe）分析其是否符合作為內連接導線所要求之低電阻特性。由分析結果得知10 nm之Co-P阻障層能有效的抑制銅原子在高溫熱處理下之擴散行為與晶粒成長行為；錳原子的摻雜不僅可以有效的提高熱處理溫度且能延長熱處理溫度而不使銅原子擴散與矽基材反應生成銅矽化合物與劇烈的晶粒成長行為導致銅薄膜破裂現象之發生。

With the integrated circuit components technology node into the 100 nm generation, the barrier layer thickness of the requirements which will become more stringent, However, the PVD or CVD manufacture method has so poor step coverge and conformity in traditionally, therefore the requirement of preparation for Ta/TaN barrier layer can not be accepted in sub-nanometer generation. The atomic layer deposition and electrochemical deposition will be considered that two important manufacturing process alternatives plan in the semiconductor industry blueprint.
In this study, we use the electrochemical deposition to make thin films with non-plating way, which adopt the proprietary nickel ultrafine partides as a catalytic dense seed layer. We discuss the different between with or without 10 nm Co-P barrier layer and Mn doping or not when they under heat treatment at hight temperature. We also use the scanning electro microscope、X-ray diffractometry analysis and voltage-current characteristics of the measurement system analysis whether it can inhibit the Copper atoms in the proliferation of high-temperature heat treatment under the diffusion; and use the four-point probe analysis whether they conform to require as the low resistance of wires characteristics connected. By the results of the analysis that the 10 nm of Co-P barrier layer can effectively suppress the Copper atomic in the proliferation of hight-temperture heat treatment under the diffusion of behavior and grain growth; the doped Mn atoms can not only effectively increase the treatment temperature but also intend the treatment times, so that can avoid Copper atom diffusion to the Silica substrate to form Cu-Si compounds, and efficiently decree the grain grouth lead to Copper film broken.

中文摘要…………………………………………………...…………….I
英文摘要………………………………………………………………...II
目錄…………………………………………………………………….III
表目錄………………………………………………………………...VI
圖目錄………………………………………………………………….VII
第1章 前言.……………………………………………………...1
第2章 文獻回顧與研究動機.………………………………….….8
2.1 銅內連接導線的材料選擇與製備……………………….8
2.1.1 傳統內連接導線之材料選擇與製備………………8
2.1.2 大馬士全面包裹內連接導線…………….………..9
2.1.3 全程濕式內連接導線…………………………….10
2.2 擴散阻障層………………………………………………11
2.3 無電鍍催化晶種與超薄阻障層之製備與應………...…13
2.4 銅合金化薄膜之材料選擇與應用…………………..…14
第3章 實驗步驟與分析技術……………………………………23
3.1 實驗步驟…………………………………...…………….23
3.1.1 SiO2基材準備……………………..…………..23
3.1.2 無電鍍析鍍前處理―電漿與化學溶液表面改質…23
3.1.3 超微密Ni晶種之吸附/還原….…………………24
3.1.4 無電鍍薄膜析鍍……………………………………25
3.1.5 電容元件試片製作…………………………………26
3.2 實驗製程設備……………………………………………26
3.3 實驗製程分析儀器………………..……….……………27
第4章 結果與討論………………………………..…………….43
4.1 鎳晶種催化銅鍍浴析鍍與超薄Co-P阻障層…………43
4.1.1 超薄Co-P阻障層熱處理行為…………….….…43
4.1.2 超微密Ni晶種催化銅鍍浴析鍍…………………44
4.2 Cu-Mn合金薄膜生長型態與微結構分析….…………47
4.2.1 Cu-Mn薄膜析鍍行為…………………….….…47
4.2.2 Cu與Cu-Mn合金薄膜長時間熱處理分析..…49
4.2.3薄膜表面型態分析…………………….…………51
4.2.4 Cu與Cu-Mn薄膜微結構分析………..………52
4.2.5薄膜電阻率與片電阻變化分析………….……53
4.3 薄膜擴散行為分析………………………………………55
4.3.1AES縱深分佈曲線分析………….………….…55
4.3.2電壓-電流分析………………….………………56
第5章 結論……………………………………………………89
未來展望………………………………………………………90
參考文獻………………………………………………

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