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研究生:林家名
研究生(外文):Chia-Min Lin
論文名稱:環繞式閘極多晶矽奈米線薄膜電晶體於結晶方法之研究
論文名稱(外文):A Study of the Crystallization Methods on Gate-All-Around (GAA) Poly-Si Nanowire Thin-Film-Transistors
指導教授:康宗貴康宗貴引用關係
指導教授(外文):Tsung-Kuei Kang
學位類別:碩士
校院名稱:逢甲大學
系所名稱:產業研發碩士班
學門:商業及管理學門
學類:其他商業及管理學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:59
中文關鍵詞:環繞閘極結構載子遷移率準分子雷射
外文關鍵詞:mobilitygate all around (GAA) structureexcimer laser
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多晶矽薄膜電晶體已廣泛應用於主動式矩陣平面顯示器的開關元件,為了要更進一步將多晶矽薄膜電晶體應用至系統面板和三維積體電路上,我們必須不斷改善電晶體的特性。載子遷移率(mobility)是影響電晶體最重要的電性之一。而晶粒尺寸(grain size)又嚴重的影響到載子遷移率。使用雷射結晶技術擴大晶粒尺寸是普遍的作法。然而晶粒的擴張有其極限,因此我們使用奈米線當通道用意是把通道縮小並落在晶粒裡進而得到接近於單晶的電性。然而當多晶矽薄膜電晶體的尺寸縮小時,由於在通道中的晶界缺陷和薄膜電晶體的浮體(floating body)結構,元件會發生一些非理想的短通道效應,像是臨界電壓下降、汲極誘導能障下降和紐結效應(kink effect)。由於多重閘極結構有極佳的閘極控制能力,且能有效抑制非理想的短通道效應。因此在本篇論文裡我們提出了兩種環繞閘極與多重奈米通道之多晶矽薄膜電晶體搭配雷射結晶與奈米寬度定義法來改善元件的電特性。
在第二章,我們先用側壁子 (spacer) 蝕刻方法定義出通道之奈米線,接者利用源極與汲極相對通道較厚之設計,在雷射能量320 mJ/cm2照射下,晶粒會從較厚的源極與汲極兩旁往中間成長,直到發生接觸而在中間產生一晶粒邊界 (grain boundary)。較薄的奈米線通道區可得到約400-nm晶粒尺寸。非常少的文獻提到奈米線形成後再結晶的方法。製作出的環繞閘極與多重奈米通道搭配準分子雷射結晶法之多晶矽薄膜電晶體和環繞閘極與多重奈米通道搭配傳統結晶法的元件比較起來,有相當良好的電特性。在電晶體導通時,我們的元件有較低的臨界電壓(由1.65到-0.94 V)、較小的汲極誘導能障下降(由0.268到0.157 V/V)、較陡峭的次臨界擺幅(由450到142 mV/decade)、較低的紐結電流、較高的導通電流(由 1.24×106到1.37×107 A)與載子移動率(由30到273 cm2/V-s)。
在第三章,我們提出第二種環繞閘極與多重奈米通道之多晶矽薄膜電晶體搭配準分子雷射結晶法,跟前法不一樣的是,本方法是先結晶完再製作奈米線通道。首先,整面的晶片(blanket wafer)用準分子雷射之連續側向固化(Sequential Laterally Solidification)結晶的方法形成大約3-µm的晶粒。接者於該大晶粒之多晶矽薄膜上,利用氮化矽側壁子當硬遮罩(hard mask)之奈米寬度定義法來製作奈米線電晶體。該法製作出的環繞閘極與多重奈米通道之多晶矽薄膜電晶體和三閘極(tri-gate)與多重奈米通道的元件比較起來有非常好的電特性,相較於未用奈米寬度定義法之連續側向固化多晶矽薄膜電晶體,我們的元件有較低的臨界電壓由(-0.25到-0.75 V)、較小的汲極誘導能障下降(由0.41到0.06 V/V)、較陡峭的次臨界擺幅(由327到109 mV/decade)、較低的紐結電流、較高的導通電流(由6.43×106到8.65×107 A)與載子移動率(由208到679 cm2/V-s)。
在這些結構中,具環繞閘極與奈米通道的多晶矽薄膜電晶體搭配準分子雷射連續側向方法展現了最好的特性。另外我們也比較不同尺寸的元件,和傳統(planar)的多晶矽薄膜電晶體相比,我們的元件有非常好載子移動率和非常有效的抑制短通道能力。
Poly-Si thin film transistors (TFTs) have been widely used as switching elements in active-matrix displays. For applications on system-on-panel (SOP) and three-dimension integrated circuits (3-D ICs), further improvement of device performance are required. The mobility is one of the most important electrical characteristic in poly-Si TFTs, which is profoundly dependent on the grain sizes within channel region. The use of excimer laser crystallization is the main approach to enlarge the grain size, but its size of grain growth is still limited. Other than crystallization, channel dimension scaled-down within a grain is another way to improve mobility performance. However, there are some undesired short-channel effects in conventional scaled poly-Si TFTs such as threshold voltage (Vth) roll-off, drain-induced barrier lowering (DIBL), and kink effect which are caused from the grain-boundary defects and the floating body in the channel region. It has been reported that multi-gate and nanowire structures have good gate controllability and thus effectively suppress the short channel effects.
In this thesis, we proposed two gate-all-around poly-Si TFTs with multiple nanowire channels (GAA-MNC TFTs) by excimer laser crystallization (ELC) and nano-width patterning techniques to enhance the device performance.
In the chapter 2, spacer patterning approaches was utilized to perform the nano-scale nanowires as channels and relatively thick regions at the source and drain islands simultaneously. The grain size in thinner nanowire channel region is around 300 nm. There is only one grain-growing seed can be performed in each end of nanowire connected to the thicker S/D islands. Therefore, high crystalline Si nanowire with only-one grain boundary in the middle of channel can be carried out. In previous works, there is few research on nanowire crystallization with excimer laser. The fabricated GAA-ELC MNC TFTs exhibit excellent electrical performance as compared to the SPC counterparts. Under the on-state operation, the GAA-MNC TFTs demonstrate lower Vth (from 1.65 to -0.94 V), smaller DIBL (from 0.268 to 0.157 V/V), sbrupt subthreshold swing (SS) (from 450 to 142 mV/decade), less kink current, higher on current (from 1.24×106 to 1.37×107 A), and higher mobility (from 30 to 273 cm2/V-s).
In the chapter 3, another gate-all-around (GAA) poly-Si TFTs structure with single-crystalline-like nanowires were proposed as well. Unlike previous method, such single-crystalline-like nanowires were directly performed with spacer patterning technique on the large-grain poly-Si which was crystallized by sequential-lateral-solidification (SLS) method. The fabricated GAA-SLS MNC TFTs exhibit excellent electrical performance as compared to CP-SLS MNC TFTs ones. The GAA-SLS MNC TFTs demonstrate lower Vth (from -0.25 to -0.75 V), smaller DIBL (from 0.41 to 0.06 V/V), stepper subthreshold swing (SS) (from 327 to 109 mV/decade), less kink current, higher on current (from 6.43×106 to 8.65×107 A), and higher mobility (from 208 to 679 cm2/V-s).
Among those, the GAA-SLS MNC TFTs display the best performance. Moreover, the GAA-SLS MNC and conventional planar (CP-SLS) TFTs with different dimensions were also discussed. The GAA-SLS MNC TFTs demonstrate excellent immunity on the short-channel effect and excellent mobility.
Contents
Abstract (in Chinese) ii
Abstract (in English) iv
Contents vi
Figure Captions viii
Table Lists x
Chapter 1
Introduction 1
1-1 An Overview of Low Temperature Poly-Si (LTPS) TFTs 1
1-2 Crystallization of Amorphous Silicon (A-Si) Thin Films 2
1-2-1 Solid Phase Crystallization 3
1-2-2 Metal Induced Crystallization 4
1-2-3 Laser Crystallization 4
1-3 Defect Passivation 7
1-4 Gate Engineering 8
1-5 Motivation 10
1-6 Thesis Outline 12
Chapter 2 Gate-All-Around (GAA) Multiple Nanowire Channels (MNC) with Excimer Laser crystallizion 14
2-1 Introduction of laser system 14
2-2 Experiment 15
2-3 Results and Discussion 16
2-4 Summary 20
Chapter 3 Gate-All-Around (GAA) Thin Film Transistors with Single-Crystalline-Like Nanowire Channels 22
3-1 Introduction 22
3-2 Experiment 23
3-3 Results and Discussion 24
3-4 Summary 26
Chapter 4 Conclusions and Recommendation 27
References 29
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Chapter 2
[2.1]Yung-Chun Wu, Chun-Yen Chang, Ting-Chang Chang., Po-Tsun Lu .Chi-Shen Chen, Chun-Hao Tu. Hsiao-Wen Zan, Ya-Hsiang Ta, and Simon Min Sze “High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels,” 778-780 IEDM, 2004.
[2.2]Yuan-Chun Wu, Cheng-Wei Chou, Chun-Hao Tu, Jen-Chung Lou, and Chun-Yen Chang, “Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization,” APPLIED PHYSICS LETTERS 87, 143504 , 2005.
[2.3]Wei Lu1,and Charles M Lieber, “Semiconductor nanowires,” J. Phys. D: Appl. Phys. 39, R387–R406, 2006.
[2.4]Jae-Hong Jeon, Min-Cheol Lee, Kee-Chan Park, and Min-Koo Han, “A New Polycrystalline Silicon TFT With a Single Grain Boundary in the Channel,” IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 9, SEPTEMBER 2001.
[2.5]Ta-Chuan Lia, Shih-Wei Tu, Ming H. Yu, Wei-Kai Lin, Cheng-Chin Liu, Kuo-Jui Chang, Ya-Hsiang Tai, and Huang-Chung Cheng, “Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels,” IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST, 2008.
[2.6]K. R. Olasupo and M. K. Hatalis, “Leakage Current Mechanism in Sub-Micron Poly silicon Thin-Film Transistors,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 8, AUGUST 1996.
[2.7]Ta-Chuan Lia, Shih-Wei Tu, Ming H. Yu, Wei-Kai Lin, Cheng-Chin Liu, Kuo-Jui Chang, Ya-Hsiang Tai, and Huang-Chung Cheng, “Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels,” IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST, 2008.
[2.8]Anurag Chaudhry and M. Jagadesh Kumar, “Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 1, MARCH 2004.
[2.9]Tor A. Fjeldly and Michael Shur, “Threshold Voltage Modeling and the Subthreshold Regime of Operation of Short-Channel MOSFET’s,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 1 , JANUARY 1993.
[2.10]S. D. Brotherton,a) C. Glasse, C. Glaister, P. Green, F. Rohlfing, and J. R. Ayres, “High-speed, short-channel polycrystalline silicon thin-film transistors,” APPLIED PHYSICS LETTERS VOLUME 84, NUMBER 2 12 JANUARY 2004.
[2.11]J. R. DAVIS, ANTHONY E. GLACCUM, “Improved Subthreshold Characteristics of n-Channel SOI Transistors,” IEEE ELECTRON DEVICE LETTERS, VOL. EDL-7, NO. 10, OCTOBER 1986.
[2.12]Mitsutoshi Miyasaka, John Stoemenos, “Excimer laser annealing of amorphous and solid-phase-crystallized silicon films,” JOURNAL OF APPLIED PHYSICS VOLUME 86, NUMBER 10 15 NOVEMBER 1999.
[2.13]J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys.53(2), February 1982.
[2.14]Yung-Chun Wu, Ting-Chang Chang, Chun-Yen Chang, Chi-Shen Chen, and Chun-Hao Tu, Po-Tsun Liu, Hsiao-Wen Zan and Ya-Hsiang Tai “High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure,” APPLIED PHYSICS LETTERS VOLUME 84, NUMBER 19 10 MAY 2004.
Chapter 3

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[3.2]Robert S. Sposili and James S. Im. “Sequential lateral solidification of thin silicon films on SiO2,”. Appl. Phys. Lett. 69 (19), 4 November, 1996.
[3.3]Ludolf Herbst, Frank Simon, Ulrich Rebhan, Rustem Osmanow, Burkhard Fechner, “New Technology for Creation of LTPS with Excimer Laser Annealing, ” Asia Display/IMID 04 Proceedings 2004.
[3.4]M. Koyanagi, T. Shimatani, M. Tsuno, T. Matsumoto, N. Kato and S. Yamada. “Evaluation of Self-Heating Effect in Poly-Si TFT Using Quasi Three-Dimensional Temperature Analysis,” IEDM. 2004.
[3.5]P. Peressini and W. S. Johnson, “THRESHOLD ADJUSTMENT OF N-CHANNEL ENHANCEMENT MODE FETs BY ION IMPLANTATION, ” Electron Devices Meeting, 1973 International, Volume: 19, 467- 468, 1973.
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