臺灣博碩士論文加值系統

隨著CMOS的尺寸進入深次微米後，IC設計在單一層晶圓變得難以再藉由縮小CMOS的尺寸來提升效能。然而3D-IC設計為這個問題帶來另一個新的方向。
在3D平面規劃中階層式設計架構的效能比先前的完全3D的平面配置的效能好。在這篇論文中，我們提出了一個新的階層式設計架構的3D平面規劃的演算法針對通孔與繞線長度的最小化。我們使用區塊分割來考慮同層以及跨層的連線。如果每個區塊裡的模組數量是適當的，那麼這個演算法能有效率的縮減繞線長度。相較於沒有使用區塊分割的繞線長度大約減少了五個百分比。

致謝…………………………………………………………………………………i
摘要………………………………………………………………………………….ii
Abstract ………………………………………………………………………….…iii
目錄………………………………………………………………………………...…iv
圖目錄……………………………………………………………………………...…vi
表目錄………………………………………………………………………….……viii
第一章 簡介……………………………………………………………………..…1
第二章 相關研究…………………………………………………………….……4
2.1 Multilevel k-way Hypergraph Partitioning……..……………………………4
2.2 B*-Tree: A New Representation for Non-Slicing Floorplans……………..…8
2.3 Multiobjective Microarchitectural Floorplanning for 2-D and 3-D IC..….10
第三章 問題描述………………………………………………………………12
3.1 研究動機…………………………………………………………….……12
3.2輸入及輸出資訊………………………………………………………..…12
3.3其他限制……………………………………………………………………15
第四章 演算法及流程介紹……………………………………………………16
4.1 方法流程…………………………………………...………………………16
4.2分層........………….…………………………………...……………………17
4.3 樓層決定………………………………………………………………...…18
4.4切割interlayer connection………………………………..…………………19
4.5分配其它的modules……………………..…………………………………21
4.6 每層Blocks位置配置…………………..…………...…………………….23
4.7 Floorplanning每一個block………………………...………………………25
4.8 虛擬碼…………………………………………………………………26
第五章 實驗數據……………………………………………..…………………28
第六章 結論………………………………………………………………………39
參考文獻……………………………………………………………..………………40

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