(3.238.173.209) 您好!臺灣時間:2021/05/16 04:23
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:蔡宗哲
研究生(外文):Tsung-Che Tsai
論文名稱:以客製化指令實現對數數字系統算術於AlteraSOPC系統及其應用
論文名稱(外文):Implementation of LNS arithmetic with custom instruction on an Altera SOPC system and its application
指導教授:陳啟鏘
指導教授(外文):Chich-yang Chen
學位類別:碩士
校院名稱:逢甲大學
系所名稱:資訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:70
中文關鍵詞:處理器特殊指令設計對數數字系統精簡指令集計算機浮點數數字系統影像追蹤
外文關鍵詞:Floating-Point (FLP) Number SystemKullback-Leibler (KL) divergenceReduced Instruction Set Computing (RISC)Logarithmic Number System(LNS)
相關次數:
  • 被引用被引用:1
  • 點閱點閱:165
  • 評分評分:
  • 下載下載:34
  • 收藏至我的研究室書目清單書目收藏:0
在算術單元的設計上,不同數字系統的選用會反應出不同的效能在電路架構、電路面積、精準度、執行速度以及電力消耗。在這研究中,我們著重在浮點數數字系統和對數數字系統下的算術單元設計。所以我們在Altera SOPC和Nios-II處理器下使用客製化指令設計方法去設計32位元浮點數和對數算術指令,這些指令包括加法、減法、乘法、除法、平方、開方和指數運算( ),而且我們也去比較兩算術系統的效能。
我們發現在對數乘法、除法、平方、開方和指數運算( )中,相較於浮點數運算會有比較好的效能。然而,對數加、減法指令將會導致大量的硬體和時間消耗。為了解決這個問題,我們參考精簡指令集計算機的原理,提出一個方法來設計對數加、減法。因此,我們使用幾個短指令去實作對數加、減法,這些短指令包括最大值、指數和對數指令,而且這個方法可以達到硬體分享。換句話說,對數加、減法是透過這些指令硬體分享來運算,所以硬體的成本可以有效的縮減。
我們也將我們設計好的浮點數與對數算術指令應用在影像追蹤上,並利用Kullback-Leibler(KL)divergence取指數方法來做追蹤,而這個應用需要大量乘法、除法和指數計算。從我們的實驗結果來看,我們提出的浮點數混合對數指令方法提升的效能相較於用軟體浮點數方法可達到增快速度99.64%,對數指令方法相較於浮點數混合對數指令方法也達到增快速度5.63%。
In designing arithmetic units, the adoption of different number system will have different performance in the circuit architecture and area, accuracy, aped, and power consumption. In this research, we focused on designing the arithmetic units with two number systems, the floating-point (FLP) umber system and logarithmic number system (LNS). We used custom-instruction design method to design 32-bit FLP and LNS arithmetic instructions on an Altera system-on-programmable-chip (SOPC) system with Nios-II soft processor. The instructions include addition, subtraction, multiplication, division, square, square root, and powering ( ) operations, we can thus compare the performance of these two arithmetic system on the SOPC system.
We have found that the LNS arithmetic has better performance in multiplication, division, square, square root, and powering ( ) operations over FLP arithmetic. However, the LNS addition/ subtraction instruction will cause a lot of hardware and time delay. To solve this problem, we proposed that the principle of RISC (reduced-instruction-set-computer) be adopted in designing the LNS addition/subtraction instruction. That is, the LNS addition/ subtraction operation is performed by several short instructions which include the maximum, exponential, addition or subtraction by one, and logarithmic instructions. This approach has the benefit of hardware sharing. In other words, the hardware of these instructions is shared by LNS addition/ subtraction operation, and therefore the hardware cost is reduced.
We also applied our designed FLP and LNS custom instructions to an image tracking system. This image tracking system is based on Kullback-Leibler (KL) divergence algorithm which requires many operations of FLP multiplication, division, and powering operations. Form our experiments, we found that the implementation method with combined custom FLP and custom LNS instructions can be 99.64 percents faster than the pure FLP software method. Furthermore, the method with LNS custom-instructions 5.63 percents faster than the method with combined custom FLP and LNs instructions.
致謝 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 vii
第一章 研究計畫之動機及目的 1
1.1 研究背景 1
1.2 研究目的 2
1.3 論文架構 3
第二章 浮點數數字系統 5
2.1 浮點數算術 5
2.2 浮點數格式 5
2.3 浮點數四則運算及電路設計 7
2.3.1 浮點數加、減法原理及電路設計 7
2.3.2 浮點數乘法原理及電路設計 10
2.3.3 浮點數除法原理 13
第三章 對數數字系統 16
3.1 對數算術 16
3.2 對數格式 16
3.3 對數數字系統可表示的範圍與精準度 17
3.4 對數數字系統四則運算 19
3.4.1 對數乘、除法原理及電路設計 19
3.4.2 對數加、減法原理 21
3.5 對數系統平方、開根號運算 22
第四章 研究方法 24
4.1 設計概念 24
4.2 對數加、減法專用格式 26
4.3 對數減法所需的精準度 27
4.4 Altera SOPC系統中客製化指令設計[19] 28
4.4.1 Altera 的SOPC 28
4.4.2 Nios II 29
4.4.3 客製化指令 30
4.5 對數加、減法指令設計 37
4.6 指數函數 45
第五章 影像追蹤應用 47
5.1 HSV色彩空間以及轉換 48
5.2 Kullback-Leibler(KL) divergence 49
第六章 系統架構與實作 51
6.1 系統架構 51
6.2 自訂客製化指令 52
6.3 影像處理架構 54
第七章 實驗結果 57
7.1 硬體空間佔用結果 57
7.2 指數函數 比較測試結果 59
7.3 指令精準度 61
7.4 影像追蹤測試結果 62
第八章 結論 67
參考文獻 68
[1] G. L. Sicuranza, "On efficient implementations of 2-D digital filters using logarithmic number system, " IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, pp. 877-885, 1983.
[2] E. E. Swartzlander Jr., D. V. S. Chandra, H. T. Nagle Jr., and S. A. Starks, "Sign/logarithm arithmetic for FFT implementation," IEEE Transactions on Computers, vol. C-32, pp. 526-534, June 1983.
[3] Debasish Das, Krishnendu Mukhopadhyaya, and Bhabani P. Sinha, "Implementation of four common functions on an LNS co-processor, " IEEE Transaction on Computers, vol. 44, no. 1, pp. 155-161, Jan. 1995.
[4] T. Stouraitis and V. Paliouras, “Considering the alternatives in low-power design,” IEEE Circuits and Devices Magazine, July 2001, pp. 23-29.
[5] Israel Koren, Computer Arithmetic Algorithms, New Jersey: Prentice-Hall, Inc., 1993.
[6] D. DasSarma and D. W. Matula, “Measuring the Accuracy of ROM Reciprocal Tables,” IEEE Transactions on Computers, vol. 43, no. 8, pp. 932-940, 1994.
[7] T. A. Brubaker and J. C. Becker, “Multiplication using logarithms implemented with read-only memory,” IEEE Transactions on Computers, Vol. C-24, pp. 761-765, Aug. 1975.
[8] Chichyang Chen, Rui-Lin Chen, and Chih-Huan Yang, “Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost,” IEEE Transactions on Computers, vol. 49, no. 7, pp. 716-726, July 2000.
[9] M. L. Frey and F. J. Taylor, “A table reduction technique for logarithmically architected digital filters,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-33, no. 3, pp. 718-719, June 1985.
[10] David M. Lewis, “An architecture for addition and subtraction of long word length numbers in the logarithmic number system,” IEEE Transactions on Computers, vol. 39, no. 11, pp. 1325-1336, Nov. 1990.
[11] Lawrence K. Yu and David M. Lewis, “A 30-bit integrated logarithmic number system processor," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1433-1440, Oct. 1991.
[12] David M. Lewis, “Interleaved memory function interpolators with applications to an accurate LNS arithmetic unit,” IEEE Transactions on Computers, vol. 43, no. 8, pp. 974-982, Aug. 1994.
[13] Hartmut Henkel, “Improved addition for logarithmic number system,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no. 2, pp. 301-303, Feb. 1989.
[14] J. N. Coleman and E. I. Chester, “A 32-bit logarithmic arithmetic unit and its performance compared to floating-point,” Proceedings of 14th IEEE Symposium on Computer Arithmetic, Australia, pp. 142-151, 1999.
[15] Mark G. Arnold, Thomas A. Bailey, John R. Cowles, and Jerry J. Cupal, “Redundant logarithmic arithmetic," IEEE Transactions on Computers, vol. 39, pp. 1077-1086, Aug. 1990.
[16] Jean-Michel Muller, Alexandre Scherbyna, and Arnaud Tisserand, “Semi-Logarithmic number systems,” IEEE Transactions on Computers, vol. 47, no. 2, pp. 145-151, Feb. 1998.
[17] Fang-shi Lai and Ching-Farn Eric Wu, “A hybrid number system processor with geometric and complex arithmetic capabilities,” IEEE Transactions on Computers, vol. 40, no. 8, pp. 952-962, Aug. 1991.
[18] Chichyang Chen and Paul Chow, “Design of a versatile cost-effective hybrid
floating-point/LNS arithmetic processor,” Proceedings on ACM Great Lakes Symposium on VLSI(GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007, pp. 540-545
[19] Altera’s manual:Nios II Custom Instruction User Guide, at
http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf
[20] Altera’s manual:Using SOPC Builder& DSP Builder Tool Flow, at
http://www.altera.com/literature/an/an394.pdf
[21] 顏敏男,「一個多功能的32 位元對數數字系統算術單元在可重組式單晶片系統的設計及其應用」,碩士論文,逢甲大學資訊工程系,台中市,民國95年。
[22] C.Chen, R.-L. Chen, and M.-H. Sheu, “Fast additive normalization method for exponential computation,”IEE Proceedings on digital and Computer Techniques, vol.151,on.3,May 2004,pp.191-198.
[23] Chichyang Chen, Rui-Lin Chen, and Ming-Hwa Sheu, “A hardware algorithm for fast logarithmic computation with exponential convergence rate,”Journal of the Chinese Institute of Engineers ,vol.28,no.4,pp.749-752,July,2005.
[24] 楊嘉齊,「在Altera SOPC系統上實現影像追蹤-一個LNS算術的應用實例」,碩士論文,逢甲大學資訊工程系,台中市,民國95年。
[25] P. Perez, C. Hue, J. Vermaak, and M. Gangnet,” Color-based Probabilistic Tracking,” European Conference on Computer Vision, p. 661-675, 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top