在TaN/SiO2/HfO2/SiO2/Si 的結構中，使用功率為200W 與流量
200sccm 進行(H2 和NH3)電漿處理3 分鐘於HfO2 電荷儲存層，分別
會有4.5 伏與4 伏明顯的逆時針C-V 遲滯迴路曲線被發現。結果指出H 原子產生的相關缺陷不僅可以引發大量fixed positive charge，而且也有很多在HfO2 薄膜內的缺陷來造成電子充/放電。而N2 電漿處理遲滯的行為卻消失，由於N 原子可以修補HfO2 內部的缺陷。在電荷保持力的部分，對於H2 電漿處理，淺的捕捉電子陷阱會讓已經儲存的電子容易流失。但是在NH3 電漿處理後電子流失的速率比較緩慢，由於淺的捕捉電子陷阱可以被N原子修補。實驗結果指出在H2與NH3電漿處理的條件經過103 秒後，仍有(2 伏 ~ 3 伏)的記憶視窗被獲得。在TaN/SiO2/Pt NCs/SiO2/Si 的電容結構中，Pt 奈米晶粒MOS 電容器的電性不穩定性被發現由於存在3 種不同缺陷。阻障氧化層沉積在不規則的Pt 奈米晶粒上會引發額外的缺陷造成一些高漏電流密度的路徑，經由RTA 緻密化熱處理可以讓氧化層品質得到改善。有太多在阻障氧化層內部捕捉電子的缺陷會主導順時針的遲滯迴路曲線。歸納實驗數據可以清楚的發現，漏電流密度的高低並不是影響順/逆時針遲滯迴路的主因。若是於阻障氧化層沉積之後進行一次高溫退火700℃會有低而且穩定的漏電流密度，明顯(8 伏 ~ 10 伏)逆時針遲滯迴路寬度被獲得。無論如何，從電荷保持力量測中可知經過300 秒後的記憶視窗僅剩0.84 伏，本論文相信有很多捕捉電子的缺陷會被引發在奈米晶粒周圍的穿隧氧化層或阻障氧化層之間，由於受到熱應力的影響所致。

In the TaN/SiO2/HfO2/SiO2/Si structure, the HfO2 charge storage layer was treated by H2 or NH3 plasma treatment for 3 minutes. The power of the plasma treatment is 200 watt and the gas flow is 200 sccm.The results indicate the direction of C-V hysteresis curve is counterclockwise and the voltage is 4.5V and 4V respectively. The defects resulting from hydrogen atoms can induce the fixed positive
charges and result in charging or discharging on the HfO2 film. After N2 plasma treatment, the hysteresis phenomenon of the C-V hysteresis curve disappeared. The reason is that the defects in the HfO2 film could be passivated by nitrogen atoms. In the memory window, the electrons
stored on the film could be discharged easily after H2 plasma treatment owing to the shallow electron traps. But, the electrons do not discharge easily after NH3 plasma treatment. The reason is the shallow electron traps could be passivated by nitrogen atoms. Experimental results indicate the memory window (2V ~ 3 V) could be obtained after H2 or NH3 plasma treatment after discharging for 1000 sec.In the TaN/SiO2/Pt NCs/SiO2/Si structure, the electrical characteristic is instability due to three different defects. The blocking oxide capping on Irregularly-shaped nanocrystal can induce additional defects in the blocking oxide. The defects could cause severe high leakage currents. By RTA annealing, the
quality of blocking oxide can be improved and the leakage current was reduced. Lots of electron trapping defects in blocking oxide could cause the clockwise C-V hysteresis curves. According as the experimentalresults, the clockwise or counterclockwise C-V hysteresis curves are
independent on leakage current density. After the blocking layer was annealing at 700 ℃, the lower leakage current density and counterclockwise C-V hysteresis curves (8V ~ 10 V) were obtained.However, for the retention data, the memory window is only 0.84 V after discharging for 300 sec. It is believed that many electron trapping defects
in tunneling oxide or blocking oxide around nanocrystals were induced by thermal stress.

誌謝...............................................I
摘要...............................................III
英文摘要...........................................V
目錄...............................................VII
圖目錄.............................................X
表目錄.............................................XV
第一章 緒論........................................1
1.1 前言...........................................1
1.2 浮動閘非揮發性記憶體...........................2
1.3 SONOS非揮發性記憶體............................3
1.4 奈米晶粒非揮發性記憶體.........................5
1.5 高介電材料的選擇與應用.........................8
1.6 電漿系統.......................................11
1.6.1 電漿在半導體上的應用.........................11
1.6.2 電漿的基本原理...............................11
1.7 奈米尺寸下的量子效應...........................13
1.7.1 量子侷限效應 (Quantum Confinement Effect)....13
1.7.2 庫倫阻塞效應 (Coulomb Blockade Effect).......14
1.8 量測方法.......................................15
1.8.1 電容對電壓(C-V)特性量測......................15
1.8.2 C-V 遲滯迴路介紹.............................15
1.8.3 電流對電壓(I-V)特性量測......................17
1.8.4 歐傑電子能譜儀分析(AES)......................17
1.8.5 掃描式電子顯微鏡(SEM)........................18
1.9 研究動機.......................................19
1.10 論文架構......................................22
第二章 非揮發性記憶體的基本原理....................31
2.1 穿隧機制.......................................31
2.1.1 通道熱電子注入(Channel Hot Electron Injection)..31
2.1.2 福樂-諾德漢穿隧(Fowler-Nordheim Tunneling)......32
2.1.3 直接穿隧(Direct Tunneling)......................32
2.2 過度抹除(Over-Erase)..............................33
2.3 電荷保持力(Charge Retention)......................34
2.4 耐久度(Endurance).................................35
第三章 藉製程改變對電荷儲存效應之研究.................38
3.1 電漿製程對ＭＯＨＯＳ電容儲存層之研究..............38
3.1.1 實驗步驟........................................38
3.1.2 結果與討論......................................39
3.2 退火製程於電荷儲存層對奈米晶粒電容之研究..........60
3.2.1 實驗步驟........................................60
3.2.2 結果與討論......................................60
3.3 退火製程於阻障氧化層對奈米晶粒電容之研究..........81
3.3.1 實驗步驟........................................81
3.3.2 結果與討論......................................81
第四章 結論...........................................93
4.1 電漿製程對ＭＯＨＯＳ電容儲存層之研究..............93
4.2 退火製程於電荷儲存層對奈米晶粒電容之研究..........93
4.3 退火製程於阻障氧化層對奈米晶粒電容之研究..........94
參考文獻..............................................95

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