(3.237.48.165) 您好!臺灣時間:2021/05/09 12:49
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:廖緯麟
研究生(外文):Wei-Lin Liao
論文名稱:電漿或熱退火處理對非揮發性記憶體元件之效應
論文名稱(外文):Effects of Plasma or Thermal Annealing Treatment on Nonvolatile Memory Devices
指導教授:吳文發康宗貴康宗貴引用關係
指導教授(外文):Wen-Fa WuTsung-Kuei Kang
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:97
語文別:中文
論文頁數:122
中文關鍵詞:記憶視窗電荷保持力遲滯迴路退火二氧化鉿電漿處理白金奈米晶粒
外文關鍵詞:PlatinumHfO2NanocrystalAnnealHysteresis loopCharge retentionMemory WindowPlasma treatment
相關次數:
  • 被引用被引用:0
  • 點閱點閱:152
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在TaN/SiO2/HfO2/SiO2/Si 的結構中,使用功率為200W 與流量
200sccm 進行(H2 和NH3)電漿處理3 分鐘於HfO2 電荷儲存層,分別
會有4.5 伏與4 伏明顯的逆時針C-V 遲滯迴路曲線被發現。結果指出H 原子產生的相關缺陷不僅可以引發大量fixed positive charge,而且也有很多在HfO2 薄膜內的缺陷來造成電子充/放電。而N2 電漿處理遲滯的行為卻消失,由於N 原子可以修補HfO2 內部的缺陷。在電荷保持力的部分,對於H2 電漿處理,淺的捕捉電子陷阱會讓已經儲存的電子容易流失。但是在NH3 電漿處理後電子流失的速率比較緩慢,由於淺的捕捉電子陷阱可以被N原子修補。實驗結果指出在H2與NH3電漿處理的條件經過103 秒後,仍有(2 伏 ~ 3 伏)的記憶視窗被獲得。在TaN/SiO2/Pt NCs/SiO2/Si 的電容結構中,Pt 奈米晶粒MOS 電容器的電性不穩定性被發現由於存在3 種不同缺陷。阻障氧化層沉積在不規則的Pt 奈米晶粒上會引發額外的缺陷造成一些高漏電流密度的路徑,經由RTA 緻密化熱處理可以讓氧化層品質得到改善。有太多在阻障氧化層內部捕捉電子的缺陷會主導順時針的遲滯迴路曲線。歸納實驗數據可以清楚的發現,漏電流密度的高低並不是影響順/逆時針遲滯迴路的主因。若是於阻障氧化層沉積之後進行一次高溫退火700℃會有低而且穩定的漏電流密度,明顯(8 伏 ~ 10 伏)逆時針遲滯迴路寬度被獲得。無論如何,從電荷保持力量測中可知經過300 秒後的記憶視窗僅剩0.84 伏,本論文相信有很多捕捉電子的缺陷會被引發在奈米晶粒周圍的穿隧氧化層或阻障氧化層之間,由於受到熱應力的影響所致。
In the TaN/SiO2/HfO2/SiO2/Si structure, the HfO2 charge storage layer was treated by H2 or NH3 plasma treatment for 3 minutes. The power of the plasma treatment is 200 watt and the gas flow is 200 sccm.The results indicate the direction of C-V hysteresis curve is counterclockwise and the voltage is 4.5V and 4V respectively. The defects resulting from hydrogen atoms can induce the fixed positive
charges and result in charging or discharging on the HfO2 film. After N2 plasma treatment, the hysteresis phenomenon of the C-V hysteresis curve disappeared. The reason is that the defects in the HfO2 film could be passivated by nitrogen atoms. In the memory window, the electrons
stored on the film could be discharged easily after H2 plasma treatment owing to the shallow electron traps. But, the electrons do not discharge easily after NH3 plasma treatment. The reason is the shallow electron traps could be passivated by nitrogen atoms. Experimental results indicate the memory window (2V ~ 3 V) could be obtained after H2 or NH3 plasma treatment after discharging for 1000 sec.In the TaN/SiO2/Pt NCs/SiO2/Si structure, the electrical characteristic is instability due to three different defects. The blocking oxide capping on Irregularly-shaped nanocrystal can induce additional defects in the blocking oxide. The defects could cause severe high leakage currents. By RTA annealing, the
quality of blocking oxide can be improved and the leakage current was reduced. Lots of electron trapping defects in blocking oxide could cause the clockwise C-V hysteresis curves. According as the experimentalresults, the clockwise or counterclockwise C-V hysteresis curves are
independent on leakage current density. After the blocking layer was annealing at 700 ℃, the lower leakage current density and counterclockwise C-V hysteresis curves (8V ~ 10 V) were obtained.However, for the retention data, the memory window is only 0.84 V after discharging for 300 sec. It is believed that many electron trapping defects
in tunneling oxide or blocking oxide around nanocrystals were induced by thermal stress.
誌謝...............................................I
摘要...............................................III
英文摘要...........................................V
目錄...............................................VII
圖目錄.............................................X
表目錄.............................................XV
第一章 緒論........................................1
1.1 前言...........................................1
1.2 浮動閘非揮發性記憶體...........................2
1.3 SONOS非揮發性記憶體............................3
1.4 奈米晶粒非揮發性記憶體.........................5
1.5 高介電材料的選擇與應用.........................8
1.6 電漿系統.......................................11
1.6.1 電漿在半導體上的應用.........................11
1.6.2 電漿的基本原理...............................11
1.7 奈米尺寸下的量子效應...........................13
1.7.1 量子侷限效應 (Quantum Confinement Effect)....13
1.7.2 庫倫阻塞效應 (Coulomb Blockade Effect).......14
1.8 量測方法.......................................15
1.8.1 電容對電壓(C-V)特性量測......................15
1.8.2 C-V 遲滯迴路介紹.............................15
1.8.3 電流對電壓(I-V)特性量測......................17
1.8.4 歐傑電子能譜儀分析(AES)......................17
1.8.5 掃描式電子顯微鏡(SEM)........................18
1.9 研究動機.......................................19
1.10 論文架構......................................22
第二章 非揮發性記憶體的基本原理....................31
2.1 穿隧機制.......................................31
2.1.1 通道熱電子注入(Channel Hot Electron Injection)..31
2.1.2 福樂-諾德漢穿隧(Fowler-Nordheim Tunneling)......32
2.1.3 直接穿隧(Direct Tunneling)......................32
2.2 過度抹除(Over-Erase)..............................33
2.3 電荷保持力(Charge Retention)......................34
2.4 耐久度(Endurance).................................35
第三章 藉製程改變對電荷儲存效應之研究.................38
3.1 電漿製程對MOHOS電容儲存層之研究..............38
3.1.1 實驗步驟........................................38
3.1.2 結果與討論......................................39
3.2 退火製程於電荷儲存層對奈米晶粒電容之研究..........60
3.2.1 實驗步驟........................................60
3.2.2 結果與討論......................................60
3.3 退火製程於阻障氧化層對奈米晶粒電容之研究..........81
3.3.1 實驗步驟........................................81
3.3.2 結果與討論......................................81
第四章 結論...........................................93
4.1 電漿製程對MOHOS電容儲存層之研究..............93
4.2 退火製程於電荷儲存層對奈米晶粒電容之研究..........93
4.3 退火製程於阻障氧化層對奈米晶粒電容之研究..........94
參考文獻..............................................95
[1] Timothy R. Oldham, Mohammed Suhail, Peter Kuhn, Erwin Prinz, Hak S. Kim, and Kenneth A. LaBel, “Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 52, NO. 6, pp.2366-2371 DECEMBER (2005).
[2] 楊宗元, “高介電材料及奈米微晶粒捕陷層在快閃記憶體之研究”, 國立交通大學電子研究所碩士班, 中華民國95年6月.
[3] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., 46, 1288 (1967).
[4] Chih-Yuan Lu, Tao-Cheng Lu, and Rich Liu, “NON-VOLATILE MEMORY TECHNOLOGY - TODAY AND TOMORROW”, IEEE,
Proceedings of 13th IPFA, Singapore , pp. 18-23 (2006).
[5] Jan De Blauwe, “Nanocrystal Nonvolatile Memory Devices”, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 1, pp.72-77 MARCH (2002).
[6] Mori, E. Sakagami, H. Araki, Y. Kaneko, K. Narita, Y.Ohshima, N. Arai and K. Yoshikawa, “ONO Inter-poly Dielectric Scaling for Nonvolatile Memory Applications”, IEEE Transactions on Electron Device, Vol.38 NO.2, FEB (1991).
[7] Jiankang Bu and Marvin H. White, “Electrical characterization of ONO triple dielectric in SONOS nonvolatile memory devices ”, Solid-State Electronics 45, pp. 47-51 (2001).
[8] PAOLO PAVAN, ROBERTO BEZ, PIERO OLIVO AND ENRICO
ZANONI, “Flash Memory Cells-An Overview”, PROCEEDING
OF THE IEEE, VOL. 85, NO. 8, pp. 1248-1271 AUGUST (1997).
[9] T. Sugizaki, M. Kohayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer”, Symposium on VLSl Technology Digest of Technical Papers, pp. 27-28 (2003).
[10] Y. N. Tan, W. K. Chim,z B. J. Cho, and W. K. Choi, “A
MONOS-Type Flash Memory Using a High-k HfAlO Charge
Trapping Layer”, Electrochemical and Solid-State Letters, 7 (9) , pp. G198-G200 (2004).
[11] Yan-Ny Tan, Wai-Kin Chim, Byung Jin Cho, and Wee-Kiong Choi, “Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 7, pp. 1143-1147 JULY (2004).
[12] Yan Ny Tan, Wai Kin Chim, Wee Kiong Choi, Moon Sig Joo, and Byung Jin Cho, “Hafnium Aluminum Oxide as Charge Storage andBlocking-Oxide Layers in SONOS-Type Nonvolatile Memory for High-Speed Operation”, IEEE TRANSACTIONS ON
ELECTRON DEVICES, VOL. 53 NO. 4 , pp. 654-662 APRIL
(2006).
[13] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D.Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” in IEDM Tech. Dig., pp. 521-524 (1995).
[14] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory”, Appl. Phys. Lett., vol. 68, p. 1377 (1996).
[15] R. Muralidhar et al., IEEE IEDM Tech. Dig., 601 (2003).
[16] Kwangseok Han, Ilgweon Kim, and Hyungcheol Shin,
“Programming characteristics of p-channel Si nano-crystal
memory” ,IEEE Electron Device Lett. vol. 21, pp. 313–315 June (2000).
[17] Hussein I. Hanafi, Sandip Tiwari and Imran Khan, “Fast and long retention-time nano-crystal memory”, IEEE Trans. Electron Devices, vol. 43, pp. 1553–1558 Sept. (1996).
[18] Ya-Chin King, Tsu-Jae King, and Chenming Hu, “A Long-Refresh Dynamic/Quasi-Nonvolatile Memory Device with 2-nm Tunneling Oxide”, IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 8,pp. 409-411 AUGUST (1999).
[19] Ya-Chin King, Tsu-Jae King and Chenming Hu,“Charge-Trap Memory Device Fabricated by Oxidation of Si1-xGex”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4,
pp. 696-700 APRIL (2001).
[20] J. De Blauwe, M. Ostraat, M. L. Green, G. Weber, T. Sorsch, A. Kerber, F. Klemens, R. Cirelli, E. Ferry, J. L. Grazul, F. Baumann, Y. Kim, W. Mansfield, J. Bude, J. T. C. Lee, S. J. Hillenius, R. C. Flagan, and H. A. Atwater, “A novel, aerosol-nanocrystal floating-gate device for non- volatile memory applications”, in IEDM Tech. Dig., pp. 683–686 (2000).
[21] Zengtao Liu, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, “Metal Nanocrystal Memories—Part I: DeviceDesign and Fabrication”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 9, pp. 1606-1613
SEPTEMBER (2002).
[22] Chungho Lee, Anirudh Gorur-Seetharam and Edwin C. Kan,
“Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single- and Double-Layer Metal Nanocrystals”, in IEDM Tech, pp. 557-560 (2003).
[23] M. Kanoun, and A. Souifi, T. Baron and F. Mazen, “Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications”, APPLIED PHYSICS LETTERS VOLUME 84, NUMBER 25, pp. 5079-5081 (21) JUNE (2004).
[24] J. H. Stathis and D. J. DiMaria, “Reliability Projection for Ultra-Thin Oxides at Low Voltage”, IEEE International Electron Devices Meeting (IEDM ''98), San Francisco, pp. 167 (1998).
[25] D. A. Buchanan, “Scaling the gate Dielectric : Materials, Integration, and Reliability”, IBM J. Res. Develop., vol.43, No.3, p. 245 (1999).
[26] N. Yang, W. K. Henson, and J. J. Wortman, “Analysis of Tunneling Currents and Reliability of MOSFET’s with Sub-2 nm Gate Oxides”, IEEE International Electron Devices Meeting (IEDM ''99), Washington D.C., p. 453 (1999).
[27] B. H. Lee, L. kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee, “Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application”, IEEE International Electron Devices Meeting (IEDM ''99), Washington D.C., p. 133 (1999).
[28] W. Qi, R. Nich, B. Lee, L. Kang, Y. Jeon, K. Onishi, T. Ngai, S. Barieilee and J. Lee, “MOSCAP and MOSFET Characteristics Using ZrO, Gate Dielectric Deposited Directly on Si”, IEEE International Electron Devices Meeting (IEDM ''99), Washington D.C., pp.145 (1999).
[29] Y. Ma, Y. Ono, L. Stecker, D. R. Evans, and S. T. Hsu, “Zirconium Oxide Based Gate Dielectrics with Equivalent Oxide Thickness of Less Than 1.0 nm and Performance of Submicron MOSFET Using a Nitride Gate Replacement Process”, IEEE International Electron
Devices Meeting (IEDM ''99), Washington D.C., p. 149 (1999).
[30] S. J. Lee, H. F. Luan, W. P. Bai, C. H. Lee, T. S. Jeon, Y. Senzaki , D. Roberts, and D. L. Kwong, “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode”, IEEE International Electron Devices Meeting (IEDM ''00), San Francisco, p. 31(2000).
[31] B. H. Lee, R. Choi, L. Kang, S. Gopalan, R. Nieh, K. Onishi, Y. Jeon, W. J. Qi, C. Kang and J. C. Lee, “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8��-12��)”, IEEE International Electron Devices Meeting (IEDM ''00), San Francisco, p. 39 (2000).
[32] G. D. Wilk, R. M. Wallace and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations”, JOURNAL OF APPLIED PHYSICS, VOLUME 89, NUMBER 10, pp. 5243-5275 (15) MAY (2001).
[33] Stephen Hall, Octavian Buiu, Ivona Z, Mitrovic, Yi Lu and Willian M.Davey, “Review and perspective of high-k dielectrics on silicon”, JOURNAL OF TELECOMMUNICATIONS AND
INFORMATION TECHNOLOGY, pp. 33-43, (2007).
[34] K. Kukli, J. Niinisto , A. Tamm , J. Lu , M. Ritala , M. Leskela , M. Putkonen , L. Niinisto , F. Song , P. Williams and P. N. Heys, “Atomic layer deposition of ZrO2 and HfO2 on deep trenched and planar silicon”, Microelectronic Engineering 84 , pp. 2010-2013,
(2007).
[35] Hong Xiao 原著;羅正忠和張鼎張譯, “半導體製程技術導論”, 台灣培生教育出版, pp. 221-239 民國91 年.
[36] Weihua Guan, Shibing Long, Ming Liu , Qi Liu, Yuan Hu, Zhigang Li and Rui Jia, “Modeling of retention characteristics for metal and semiconductor nanocrystal memories”, Solid-State Electronics 51, pp. 806–811 (2007).
[37] Min She and Tsu-Jae King,” Impact of Crystal Size and Tunnel Dielectric on Semiconductor Nanocrystal Memory Performance” ,IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50,NO. 9, pp. 1934-1940 SEPTEMBER (2003).
[38] 汪建民, “材料分析”,中國材料科學學會.
[39] D. Y. Cho, J. M. Lee, S. J. Oh, H. Jang, J. Y. Kim, J. H. Park and A.Tanaka,“ Influence of oxygen vacancies on the electronic structure of HfO2 films”, PHYSICAL REVIEW B vol.76, 165411 Oct. (2007).
[40] T. K. Kang, C. W. Chen, C. L. Lin, and W. F. Wu, “Study of Annealing and Plasma Process on Analog Characteristics for High-k Material Capacitors”, J. Appl. Phys., (47) 5374 (2008).
[41] K. Xiong, J. Robertson and S. J. Clark, “Passivation of oxygen vacancy states in HfO2 by nitrogen”, JOURNAL OF APPLIED PHYSICS 99, 044105 (2006).
[42] Jeon-Ho Kim, Kyu-Jeong Choi and Soon-Gil Yoon, “Electrical and reliability characteristics of HfO2 gate dielectric treated in N2 and NH3 plasma atmosphere”, Applied Surface Science, pp. 313-317 242 (2005).
[43] P. W. Peacock and J. Robertson, APPLIED PHYSICS LETTERS, 83, NUMBER 10 (2003).
[44] N. J. Seong and S. G. Yoon, APPLIED PHYSICS LETTERS 87, 132903 (2005).
[45] J. L. Gavartina and A. L. Shluger, JOURNAL OF APPLIED
PHYSICS 97, 053704 (2005).
[46] J. Dufourcq, P. Mur, M.J. Gordon, S. Minoret, R. Coppard and T. Baron, “Metallic nano-crystals for flash memories”, Materials Science and Engineering C 27 , pp. 1496-1499 (2007).
[47] Gong-Ru Lin, Hao-Chung Kuo, Huang-Shen Lin and Chih-Chiang Kao, “Rapid self-assembly of Ni nanodots on Si substrate covered by a less-adhesive and heat-accumulated SiO2 layers”, APPLIED PHYSICS LETTERS 89, 073108 (2006).
[48] D. N. Kouvatsos, V. Ioannou-Sougleridis and A.G. Nassiopoulou, “Charging effects in silicon nanocrystals embedded in SiO2 films”, Materials Science and Engineering B 101, pp. 270-274 (2003).
[49] Dengtao Zhao, Yan Zhu and Jianlin Liu, “Charge storage in a metal–oxide–semiconductor capacitor containing cobalt nanocrystals”, Solid-State Electronics 50 , pp.268-271 (2006).
[50] Ch. Sargentis, K. Giannakopoulos, A. Travlos, N. Boukos and D. Tsamakis, “Simple method for the fabrication of a high dielectric constant metal-oxide-semiconductor capacitor embedded with Pt nanoparticles”, APPLIED PHYSICS LETTERS 88, 073106 (2006).
[51] J. Dufourcq, S. Bodnar, G. Gay, D. Lafond, P. Mur, G. Molas, J. P. Nieto, L. Vandroux, L. Jodin, F. Gustavo and Th. Baron, “High density platinum nanocrystals for non-volatile memory applications”, APPLIED PHYSICS LETTERS 92, 073102 (2008).
[52] H. Bachhofer, H.Reisinger, E.bertagnolli and H. von philipsborn, “Transient conduction in multidielectric silicon-oxide-nitride-oxide semiconductor structures”, JOURNAL OF APPLIED PHYSICS , VOLUME 89, NUMBER 5, 1 MARCH (2001).
[53] Marvin H. White, Dennis A. Adams, James R. Murray, Stephen Wrazien, Yijie (Sandy) Zhao1, Yu (Richard) Wang, Bilal Khan, Wayne Miller and Rajiv Mehrotra, Characterization of Scaled SONOS EEPROM Memory Devices for Space and Military Systems”, IEEE, pp. 51-58, (2004).
[54] L. Pantisano, E. Cartier, A. Kerber, R. Degraeve, M. Lorenzini, M. Rosmeulen, G. Groesenken and H. E. Maes, Tech. Dig. VLSI (2003).
[55] K. Torii, K. Shirashi, S. Miyazaki, K. Yamabe, M. Boero, T. Chikyow, K. Yamada, H. Kitajima and T. Arikado, Tech. Dig. IEDM, 129 (2004).
[56] S. Zafar, A. Kumar, E. Gusev and E. Cartier, IEEE Trans. Dev. Mater. Reliab. 5, 45 (2005).
[57] K. Xiong, J. Robertson, M.C. Gibson and S.J. Clark, Appl. Phys. Lett. 87, 183505 (2005).
[58] C. Lee, J. Choi, M. CHO, J. Park, C. S. Hwang and H. J. Kim, JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 22,
1838 (2004).
[59] P. W. Peacock and J. Robertson, APPLIED PHYSICS LETTERS 83, p. 2025 (2003).
[60] D.M. Fleetwood, “Effects of hydrogen transport and reactions on microelectronics radiation response and reliability”, Microelectronics Reliability 42, pp.523–541 (2002).
[61] Vikkram J. Kapoor, Robert S. Bailey and Herman J. Stein, “Hydrogen-related memory traps in thin silicon nitride films”, J. Vac. Sci Technol. A, Vol. 1, No. 2, pp.600-603, Apr.-June (1983).
[62] H. k. Sii, J. F. Zhang, R. Degraeve and Groeseneken, “Relation between hydrogen and generayion of interface state precursors”, Microelectronic Engineering 48, pp. 135-138 (1999).
[63] Chang-Hee Cho, Baek-Hyun Kim, Tae-Wook Kim, Seong-Ju Park Nae-Man Park and Gun-Yong Sung, “Effect of hydrogen
passivation on charge storage in silicon quantum dots embedded in silicon nitride film”, APPLIED PHYSICS LETTERS 86, 143107 (2005).
[64] Jer Chyi Wang , De Ching Shie, Tan Fu Lei and Chung Len Lee, “Characterization of Temperature Dependence for HfO2 Gate Dielectrics Treated in NH3 Plasma”, ELECTROCHEMICAL AND SOLID STATE LETTERS, pp. F34-F36 6 (10) (2003).
[65] S. Due�狒s, H. Cast�鴨, H. Garc�朦, A. G�曠ez, L. Bail�曝, K. Kukli, J. Aarik,b M. Ritala, and M. Leskel��, “Comparative Study of Flatband Voltage Transients on High-k Dielectric-Based Metal –Insulator–Semiconductor Capacitors”, Journal of The Electrochemical Society, pp. G241-G246 155 (11) (2008).
[66] Ying Qian Wang, Wan Sik Hwang, Gang Zhang, Ganesh Samudra, Yee-Chia Yeo and Won Jong Yoo, “Electrical Characteristics of Memory Devices With a High-k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 10, OCTOBER (2007).
[67] Jiun-Yi Tseng, Cheng-Wei Cheng, Sheng-Yu Wang, Tai-Bor Wu, Kuang-Yeu Hsieh and Rich Liu, “Memory characteristics of Pt nanocrystals self-assembled from reduction of an embedded PtOx ultrathin film in metal-oxide-semiconductor structures”, APPLIED PHYSICS LETTERS, VOLUME 85, NUMBER 13 (27), pp. 2595-2597 SEPTEMBER (2004).
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊
 
系統版面圖檔 系統版面圖檔