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研究生:陳奕儒
研究生(外文):Yi-Ju Chen
論文名稱:無扭結效應之金屬延伸場板複晶矽薄膜電晶體之研究
論文名稱(外文):The Study of Kink-Free Poly-Si Thin-Film Transistors Employing Extended Metal Pad
指導教授:簡鳳佐簡鳳佐引用關係
指導教授(外文):Feng-Tso Chien
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:66
中文關鍵詞:複晶矽薄膜電晶體場板漏電流扭結效應
外文關鍵詞:Poly-Si TFTfield plateleakage currentkink effect
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複晶矽薄膜電晶體由於它的高場效遷移率極驅動電流,廣泛地應用在各領域,包含主動式液晶顯示器、太陽能電池及三維積體電路。這些元件被預期可以應用在大型積體電路且製作在玻璃基板上。我們知道元件在汲極端的高電場導致了許多不理想效應,如漏電流效應、扭結效應、熱載子效應。在本篇論文中,一個高效能的的下部閘極薄膜電晶體伴隨著汲極延伸場版被發表且展示。場板可以散開汲極端的電場且改變電子流的流向來降低載子游離解離的行為。我們也使用ISE-TCAD模擬軟體來模擬場板元件的電場、電子流密度及載子的游離解離的散佈情形來分析此元件的特性。我們的實驗結果展示場板元件擁有比傳統型高的導通電流,並且也改善了扭結效應極漏電流效應。此外,在元件的穩定性方面,在施加高偏壓應力下,由於汲極延伸場板的設計,臨界電壓的漂移及轉導的衰退都因此改善了。此使電場與電流分離的場板結構在元件尺寸縮小化下也有較好的特性。
Polycrystalline silicon thin-film transistors(Poly-Si) are widely used in various field, including active-matrix liquid crystal displays(AM-LCDs), solar cells and three-dimensional(3-D) integrated circuit because of their high carrier mobility and driving current. It is expected that these devices can be fabricated on insulating substrate for the manufacturing and applications of large-area microelectrons. It is widely known that the high electric field induced near the drain causes several undesirable effects in the device electrical characteristics, including the large leakage current, kink effect, and hot carrier effect. In this thesis, a high-performance bottom-gated polycrystalline thin-film transistor with drain extend field plate is proposed and demonstrated. The field plate can spread the drain electric field out and change the electron current path to reduce the impact ionization near the drain area. We also use ISE-TCAD to simulate the electric field, electron current density, and impact ionization distributions of the proposed TFT structure to investigate the device performances. Our experimental results show that the on-current of the proposed TFT is higher than that of the conventional structure, and the kink effect and leakage current are improved simultaneously. In addition, the device stability, such as threshold voltage shift and transconductance degradation under a high gate bias is also improved by the design of drain extended field plate. The current and electric field splited structure of the proposed TFT is also beneficial to scaling down the device for a better performance.
目 錄
致謝………………………..………………………………….…….....i
中文摘要…………………………………………………..….…......ii
英文摘要……………………………………………………………iii
目錄………………………………………………………………......iv
圖目錄……………………………………………………..………...vi
表目錄………………………………………………………………viii
第一章 前言………………………………...……………………..1
1-1 薄膜電晶體簡介與應用…………………..……………….1
1-2 複晶矽薄膜電晶體之關鍵製造技術………..……...…...4
1-3 複晶矽薄膜電晶體之基本結構……………….…………6
1-4 動機……………...……………………………...……………..7
1-5 論文架構………………………………...……………………8
第二章 不理想效應與文獻回顧.............................................9
2-1 不理想效應………………………………….…...……….......9
2-1.1 漏電流效應(Leakage Current)...................................10
2-1.2 扭結效應(Kink Effect)……………..………………...12
2-1.3 熱載子效應(Hot Carrier Effect)….......……………..14
2-2 相關降電場結構之研究……..……………………………19
2-2.1 Bottom gate TFT with self-aligned Lightly Doped Drain.…….....……………………………………………19
2-2.2 OBG-UCRSD-TFT……..……………………………...20
2-2.3 汲極延伸覆蓋場板…………………………………...21第三章 汲極延伸覆蓋場板之模擬分析…………............22
3-1 前言………………………...…………………….….….........22
3-2 汲極延伸覆蓋場板之結構………….………………........22
3-3 模擬分析與討論…………….……......................................23
3-4 場板長度變化的影響………………………………………..32
3-5 保護層(passivation)厚度對場板的影響…………………….34
第四章 實作與結果討論……………......................................43
4-1 前言………………………………….……………………….43
4-2 實驗製程步驟…………………………….……………..........43
4-3 電性參數之萃取…………………………………….…......48
4-4 結果與討論……………………………………………………52
4-4.1 場板元件對偏壓應力的影響………..……………….55
4-4.2 場板元件對崩潰電壓的影響.………..……..……...58
第五章 結論……………………..…………………….…………60
參考文獻………………………..……………………………………61
圖目錄
圖1.1 薄膜電晶體之基本結構圖………..…………………………..7
圖2.1 三種不理想效應……..………………………………………..9
圖2.2 漏電流效應的機制………………………………………..….12
圖2.3 扭結效應………………………………………………………14
圖2.4 扭結效應之寄生BJT與扭結電流……………………………14
圖2.5 熱載子效應……………………………………………………18
圖2.6 CHE&DAHC………………………………...………………....18
圖2.7 Bottom gate TFT with self-aligned Lightly Doped Drain ...........20
圖2-8 OBG-UCRSD-TFT……………………………………………..21
圖3.1傳統型bottom gate結構(a)與汲極延伸場板結構圖(b)…..23
圖3.2傳統型電場分佈圖…….……………………………………….24
圖3.3場板0.5μm電場分佈圖……………………………………….25
圖3.4傳統型電子流密度分佈圖…………………………….………..25
圖3.5場板0.5μm電子流密度分佈圖……………………………….26
圖3.6傳統型載子碰撞分佈圖……………....…………………………26
圖3.7場板0.5μm載子碰撞分佈圖........................................................27
圖3.8傳統型電場3D曲線圖....………………………………………..27
圖3.9場板0.5μm電場3D曲線圖…………………………………….28
圖3.10傳統型電子流密度3D曲線圖……………………………….28
圖3.11場板0.5μm電子流密度3D曲線圖…………………………29
圖3.12傳統型載子碰撞3D曲線圖………………………………….29
圖3.13場板0.5μm載子碰撞3D曲線圖............................................30
圖3.14傳統型之電洞濃度散佈圖…………………............................31
圖3.15場板0.5μm之電洞濃度散佈圖................................................31
圖3.16場板0.3μm載子碰撞分佈圖…………………………………32
圖3.17場板0.5μm載子碰撞分佈圖.....................................................33
圖3.18場板0.75μm載子碰撞分佈圖…………………………………33
圖3.19場板1.0μm載子碰撞分佈圖......................................................34
圖3.20保護層厚度200nm的電場分佈圖.............................................35
圖3.21保護層厚度50nm的電場分佈圖...............................................35
圖3.22保護層厚度200nm的電子流密度分佈圖……………………..36
圖3.23為保護層厚度50nm的電子流密度分佈圖...............................36
圖3.24為保護層厚度200nm的載子碰撞分佈圖…………………….37
圖3.25為保護層厚度50nm的載子碰撞分佈圖...................................37
圖3.26 保護層厚度200nm的3-D電場分佈圖………………………38
圖3.27 保護層厚度50nm的3-D電場分佈圖………………………..39
圖3.28保護層厚度200nm的3-D電子流密度分佈圖……………….39
圖3.29為保護層厚度50nm的3-D電子流密度分佈圖……………..40
圖3.30為保護層厚度200nm的3-D載子碰撞分佈圖………………40
圖3.31為保護層厚度50nm的3-D載子碰撞分佈圖………………..41
圖3.32 保護層厚度200nm之電洞濃度散佈圖………………………41
圖3.33 保護層厚度50nm之電洞濃度散佈圖......................................42
圖4.1關鍵製程步驟圖............................................................................46
圖4.2 場板0.5um的俯視圖……………………………………………47
圖4.3 場板0.5μm的crossection圖.......................................................47
圖4.4 passivation 200nm 轉換曲線……………………………………52
圖4.5 passivation200nm 輸出曲線…………………………………….53
圖4.6 passivation 50nm 轉換曲線……………………………………..54
圖4.7 passivation 50nm 輸出曲線..........................................................54
圖4.8 場板元件與傳統型受偏壓應力效應後的臨界電壓漂移曲線...57
圖4-9場板元件與傳統型受偏壓應力效應後gm degradation特性圖..58
圖4-10場板元件與傳統型再不同元件大小之崩潰電壓曲線..............59

表目錄
表4-1 RSDIS-TFT與傳統型之關鍵參數………………………………55
參考文獻
[1-1] S. Gauza, X. Zhu, W. Piecek, R. Dabrowski, and S. T. Wu, “Fast Switching Liquid Crystals for Color-Sequential LCDs,” J. Display Technol., Vol.3, No.3 pp.250-252, Sep. 2007.
[1-2] J. S. Chen, and M. D. Ker, Senior, “New Gate-Bias Voltage-Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process,” J. Display Technol., pp.309-314, Vol.3 No.3, Sept. 2007.
[1-3] B. Atwood, T. Ishii, T. Osabe, T. Mine, F. Murai, K. Yano, “SESO Memory: A CMOS compatible high density embedded momory technology for mobile applications,” in Proc. Symp. VLSI Circuits, 2002, pp.154-155.
[1-4] S. C. Chen et al., “A Novel Nanowire Channel Poly-Si TFT
Functioning as Transistor and Nonvolatile SONOS Memory,” IEEE
Electron Device Letter., Vol.28, No.9, pp.809-811, Sept. 2007.
[1-5] 紀國鍾,鄭晃忠 編著“液晶顯示器技術手冊”台灣電子材料與元件協會 p.6-8, 2004.
[1-6] K. Werner, “The flowering of flat displays,”IEEE Spectrum, Vol.34,
pp.40-49,1997.
[1-7] T. J. Konno, R. Sinclair, “Metal-contact induced crystallization of semiconductors”, Materials ScienceEngineering, vol. A179~180, 1994.
[1-8] L. Hultman, A. Robertsson and H. T. G. Hentzell, “Crystallization of Amorphous Silicon During Thin-Film Gold Reaction”J. Appl. Phys. 62(9), pp.3647-3655, Nov. 1, 1987.
[1-9] G. Radnoczi et al., “Al induced crystallization of a-Si”, Journal of Applied physics, vol.69, No. 9, pp. 6394-6299, May 1991.
[2-1] M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistor and Poly-Si Thin Film Transistors,” Jpn. J. Appl. Phys., Vol.31, pp.206-209, 1992
[2-2] J. G. Fossum, A. Oritz-Conde, H. Shichijo, and S. K. Banerjee, “Anomalous leakage current in LPCVD polysilicon MOSFET’s,” IEEE Trans. Electron Devices, Vol.32, pp.1878-1884, 1985
[2-3] K. R. Olasupo, M. K. Hatalis, “Leakage current mechanism in sub-micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, Vol.43, pp.1218-1223, 1996
[2-4] M. Lack, I. W. Wu, T. J. King, A. G. Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” in IEDM Tech. Dig., 1993, pp385-388
[2-5] M. Hack and A.G. Lewis, “Avalanche-Induced Effects in Poly silicon Thin-Film Transistors,” IEEE Electron Device Lett., Vol.12 No.5, May 1991
[2-6] A. Valletta, P. Gaucci, L. Mariucci, G. Fortunato, “Modeling velocity saturation and kink effects in p-channel polysilicon thin-film transistors,” Thin Solid Films, Vol.515, pp.7417-7421, 2005
[2-7] 陳志強 編著 “LTPS低溫複晶矽顯示器技術”全華科技圖書股份有限公司 P.3-11~3-13 2004
[2-8] D. D. Venutoa, M. J. Ohletzb, “Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits,” Microelectronics Journal, Vol.34 pp.889-895, 2003
[2-9] S. Bindra, S. Haldar, R. S. Gupta, “Modeling of kink effect in polysilicon thin film transistor using charge sheet approach,” Solid-State Electronics, Vol.47, pp.645-651, 2003
[2-10] A. K. K.P., J. K. O. Sin, C. T. Nguyen, and P. K. Ko, “Kink-Free Polycrystalline Silicon Double-Gate Elevated-Channel Thin-Film Transistors,” IEEE Trans. Electron Device, Vol.45, No.12, Dec. 1998
[2-11] P. Y. Kuo, T. S. Chao, and T. F. Lei, “Suppression of the Floating-Body Effect in Poly-Si Thin-Film Transistors With Self-Aligned Schottky Barrier Source and Ohmic Body Contact Structure,” IEEE Electron Device Lett., Vol.25 No.9, Sep. 2004
[2-12] C., W. Kin, “Semiconductor device and failure analysis : using photon emission microscopy,” Chichester, [England]; New York : Wiley, c2000
[2-13] T. E. “Hot carrier effects in sub micrometer MOS VLSIs,” Proc. IEEE, 131, p.153
[2-14] E. Takeda, N. Suzuki, and T. Hagiwara, “Device Performance Degradation to Hot-Carrier Injection at Energies Below the Si-SiO2 Energy Barrier,” in Proc. Intl. Electron Devices Meeting, pp.396-399, 1983
[2-15] Nakagome, E. Takeda, H. Kume, and S. Asai, “New observation of hot-carrier injection phenomena,” Jpn. J. Appl. Phys. Vol.22, Supplement 22-1, pp.99-102 (1983)
[2-16] E. Takeda, C. Y. Yang, A. M. Hamada, “Hot-Carrier Effects in MOS Devices,” Academic Press, 1995. Chapter 2
[2-17] A. K. K.P., J. K. O. Sin, C. T. Nguyen, and P. K. Ko, “Kink-Free Polycrystalline Silicon Double-Gate Elevated-Channel Thin-Film Transistors,” IEEE Trans. Electron Device, Vol.45, No.12, Dec. 1998
[2-18] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, K. Natori, “Analysis of the Drain Breakdown Mechanism in Ultra-Thin-Film SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol.37, No.9, Sep. 1990
[2-19] Chun-Ting Liu, Chen-Hua Douglas Yu, Avi Kornblit, Kuo-Hua Lee, “Inverted Thin-Film Transistors with a simple Self-Aligned Lightly Doped Drain Structure” IEEE Trans. Electron Devices, Vol.39, No.12, Dec. 1992
[2-20] I.-S. Kang, S.-H. Han, S.-K. Joo, “Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Siurce/Drain” IEEE Electron Device Letter., Vol.29, No.3, pp.232-234, March. 2008.
[3-1] ISE-TCAD Manuals, release 10.0
[3-2]A. G. Chynoweth,“Ionization rates for electrons and holes in silicon”Phys. Rev., vol. 109, pp. 1537-1540, 1958.
[4-1] 陳志強 編著“LTPS低溫複晶矽顯示器技術” 全華科技圖書股份有限公司 p.2-05~2-07 2004
[4-2] N. I. Lee, J. W. Lee, H. S. Kim, and C. H. Han, “High-Performance EEPROM’s Using N- and P-Channel Polysilicon Thin-Film Transistors with Electron Cyclotron Resonance N O-Plasma Oxide,” IEEE Electron Device Lett., vol. 20, no. 1, Jan. 1999
[4-3] J. H. Oh, H. J. Chung, N. I. Lee, and C. H. Han, “A High-Endurance Low-Temperature Polysilicon Thin-Film Transistor EEPROM Cell,” IEEE Electron Device Lett., vol. 21, no. 6, Jun. 2000.
[4-4] D. K. Schroder, “Semiconductor Material and Device Characterization,” Second Edition, Ch. 8, p-500.
[4-5] Y. C. Wu egt al. ,“Effects of Channel With on Electrical Characteristics of Polysilicon TFTs with Multiple Nanowire Channels,” IEEE Trans. Electron Devices, vol. 52, no. 10, Oct. 2005.
[4-6] M. C. Wang et al. , “Analysis of Parasitic Resistance and Channel Sheet Conductance of a-Si:H TFT under Mechanical Bending,” Electrochem. Soc., 103, J49-J51, 2007.
[4-7] S. Zhang, C. Zhu, J. K. O. Sin, and P. K. T. Mok, “A Novel Ultrathin Elevated Channel Low-Temperature Poly-Si TFT,” IEEE Electron Device Lett., vol. 20, no. 11, Nov. 1999.
[4-8] S. Zhang, C.g Zhu, J. K. O. Sin, J. N. Li, and P. K. T. Mok, “Untra-Thin Elevated Channel Poly-Si TFT Technology for Fully-Integrated AMLCD System on Glass,” IEEE Trans. Electron Devices, vol. 47, no. 3, Mar. 2000.
[4-9] K. Ono, T. Anoyama, N. Konishi, and K. Miyata, “Analysis of current voltage characteristics of low-temperature-processed polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 39, pp. 792-802, 1992.
[4-10] B. A. Khan and R. Pandya, “Activation-energy of source-drain current in hydrogenated and unhydrogenated polysilicon thin-films transistors,” IEEE Trans. Electron Devices, vol. 37, pp. 1727-1734, 1990.
[4-11] James D. Bernstein et al., “Hydrogenation of Polycrystalline Silicon Thin Film Transistors by Plasma Ion Imdantation,” IEEE Electron Device Lett., vol. 16. no. 10, Oct. 1995.
[4-12] S. Banerjee, R. Sundaresan, H. Schichijo, and S. Malhi, “Hot-carrier degradation of n-channel polysilicon MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp. 152-157, 1988.
[4-13] M. Hack, A. G. Lewis, and I. W. Wu, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, pp.82897, 1993.
[4-14] J. W. Lee, N. I. Lee, J. I. Han, and C. H. Han, “Characteristics of Polysilicon Thin-Film Transistor with Thin-Gate Dielectric Grown by Electron Cyclotron Resonance Nitrous Oxide Plasma,” IEEE Electron Device Lett., vol. 18, no. 5, May 1997.
[4-15] H. N. Chern, C. L. Lee, and T. F. Lei, “The Effects of Fluorine Passivation on Polysilicon Thin-Film Transistor,” IEEE Trans. Electron Device, vol. 41, no. 5, May 1994.
[4-16] F. S. Wang, M. J. Tsai, and H. C. Cheng, “The effects of NH3 Plasma Passivation on Polysilicon Thin-Film Transistors,” IEEE Electron Device Lett., vol. 16, no. 11, Nov. 1995.
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