複晶矽薄膜電晶體由於它的高場效遷移率極驅動電流，廣泛地應用在各領域，包含主動式液晶顯示器、太陽能電池及三維積體電路。這些元件被預期可以應用在大型積體電路且製作在玻璃基板上。我們知道元件在汲極端的高電場導致了許多不理想效應，如漏電流效應、扭結效應、熱載子效應。在本篇論文中，一個高效能的的下部閘極薄膜電晶體伴隨著汲極延伸場版被發表且展示。場板可以散開汲極端的電場且改變電子流的流向來降低載子游離解離的行為。我們也使用ISE-TCAD模擬軟體來模擬場板元件的電場、電子流密度及載子的游離解離的散佈情形來分析此元件的特性。我們的實驗結果展示場板元件擁有比傳統型高的導通電流，並且也改善了扭結效應極漏電流效應。此外，在元件的穩定性方面，在施加高偏壓應力下，由於汲極延伸場板的設計，臨界電壓的漂移及轉導的衰退都因此改善了。此使電場與電流分離的場板結構在元件尺寸縮小化下也有較好的特性。

Polycrystalline silicon thin-film transistors(Poly-Si) are widely used in various field, including active-matrix liquid crystal displays(AM-LCDs), solar cells and three-dimensional(3-D) integrated circuit because of their high carrier mobility and driving current. It is expected that these devices can be fabricated on insulating substrate for the manufacturing and applications of large-area microelectrons. It is widely known that the high electric field induced near the drain causes several undesirable effects in the device electrical characteristics, including the large leakage current, kink effect, and hot carrier effect. In this thesis, a high-performance bottom-gated polycrystalline thin-film transistor with drain extend field plate is proposed and demonstrated. The field plate can spread the drain electric field out and change the electron current path to reduce the impact ionization near the drain area. We also use ISE-TCAD to simulate the electric field, electron current density, and impact ionization distributions of the proposed TFT structure to investigate the device performances. Our experimental results show that the on-current of the proposed TFT is higher than that of the conventional structure, and the kink effect and leakage current are improved simultaneously. In addition, the device stability, such as threshold voltage shift and transconductance degradation under a high gate bias is also improved by the design of drain extended field plate. The current and electric field splited structure of the proposed TFT is also beneficial to scaling down the device for a better performance.

目 錄
致謝………………………..………………………………….…….....i
中文摘要…………………………………………………..….…......ii
英文摘要……………………………………………………………iii
目錄………………………………………………………………......iv
圖目錄……………………………………………………..………...vi
表目錄………………………………………………………………viii
第一章 前言………………………………...……………………..1
1-1 薄膜電晶體簡介與應用…………………..……………….1
1-2 複晶矽薄膜電晶體之關鍵製造技術………..……...…...4
1-3 複晶矽薄膜電晶體之基本結構……………….…………6
1-4 動機……………...……………………………...……………..7
1-5 論文架構………………………………...……………………8
第二章 不理想效應與文獻回顧.............................................9
2-1 不理想效應………………………………….…...……….......9
2-1.1 漏電流效應(Leakage Current)...................................10
2-1.2 扭結效應(Kink Effect)……………..………………...12
2-1.3 熱載子效應(Hot Carrier Effect)….......……………..14
2-2 相關降電場結構之研究……..……………………………19
2-2.1 Bottom gate TFT with self-aligned Lightly Doped Drain.…….....……………………………………………19
2-2.2 OBG-UCRSD-TFT……..……………………………...20
2-2.3 汲極延伸覆蓋場板…………………………………...21第三章 汲極延伸覆蓋場板之模擬分析…………............22
3-1 前言………………………...…………………….….….........22
3-2 汲極延伸覆蓋場板之結構………….………………........22
3-3 模擬分析與討論…………….……......................................23
3-4 場板長度變化的影響………………………………………..32
3-5 保護層(passivation)厚度對場板的影響…………………….34
第四章 實作與結果討論……………......................................43
4-1 前言………………………………….……………………….43
4-2 實驗製程步驟…………………………….……………..........43
4-3 電性參數之萃取…………………………………….…......48
4-4 結果與討論……………………………………………………52
4-4.1 場板元件對偏壓應力的影響………..……………….55
4-4.2 場板元件對崩潰電壓的影響.………..……..……...58
第五章 結論……………………..…………………….…………60
參考文獻………………………..……………………………………61
圖目錄
圖1.1 薄膜電晶體之基本結構圖………..…………………………..7
圖2.1 三種不理想效應……..………………………………………..9
圖2.2 漏電流效應的機制………………………………………..….12
圖2.3 扭結效應………………………………………………………14
圖2.4 扭結效應之寄生BJT與扭結電流……………………………14
圖2.5 熱載子效應……………………………………………………18
圖2.6 CHE&DAHC………………………………...………………....18
圖2.7 Bottom gate TFT with self-aligned Lightly Doped Drain ...........20
圖2-8 OBG-UCRSD-TFT……………………………………………..21
圖3.1傳統型bottom gate結構(a)與汲極延伸場板結構圖(b)…..23
圖3.2傳統型電場分佈圖…….……………………………………….24
圖3.3場板0.5μm電場分佈圖……………………………………….25
圖3.4傳統型電子流密度分佈圖…………………………….………..25
圖3.5場板0.5μm電子流密度分佈圖……………………………….26
圖3.6傳統型載子碰撞分佈圖……………....…………………………26
圖3.7場板0.5μm載子碰撞分佈圖........................................................27
圖3.8傳統型電場3D曲線圖....………………………………………..27
圖3.9場板0.5μm電場3D曲線圖…………………………………….28
圖3.10傳統型電子流密度3D曲線圖……………………………….28
圖3.11場板0.5μm電子流密度3D曲線圖…………………………29
圖3.12傳統型載子碰撞3D曲線圖………………………………….29
圖3.13場板0.5μm載子碰撞3D曲線圖............................................30
圖3.14傳統型之電洞濃度散佈圖…………………............................31
圖3.15場板0.5μm之電洞濃度散佈圖................................................31
圖3.16場板0.3μm載子碰撞分佈圖…………………………………32
圖3.17場板0.5μm載子碰撞分佈圖.....................................................33
圖3.18場板0.75μm載子碰撞分佈圖…………………………………33
圖3.19場板1.0μm載子碰撞分佈圖......................................................34
圖3.20保護層厚度200nm的電場分佈圖.............................................35
圖3.21保護層厚度50nm的電場分佈圖...............................................35
圖3.22保護層厚度200nm的電子流密度分佈圖……………………..36
圖3.23為保護層厚度50nm的電子流密度分佈圖...............................36
圖3.24為保護層厚度200nm的載子碰撞分佈圖…………………….37
圖3.25為保護層厚度50nm的載子碰撞分佈圖...................................37
圖3.26 保護層厚度200nm的3-D電場分佈圖………………………38
圖3.27 保護層厚度50nm的3-D電場分佈圖………………………..39
圖3.28保護層厚度200nm的3-D電子流密度分佈圖……………….39
圖3.29為保護層厚度50nm的3-D電子流密度分佈圖……………..40
圖3.30為保護層厚度200nm的3-D載子碰撞分佈圖………………40
圖3.31為保護層厚度50nm的3-D載子碰撞分佈圖………………..41
圖3.32 保護層厚度200nm之電洞濃度散佈圖………………………41
圖3.33 保護層厚度50nm之電洞濃度散佈圖......................................42
圖4.1關鍵製程步驟圖............................................................................46
圖4.2 場板0.5um的俯視圖……………………………………………47
圖4.3 場板0.5μm的crossection圖.......................................................47
圖4.4 passivation 200nm 轉換曲線……………………………………52
圖4.5 passivation200nm 輸出曲線…………………………………….53
圖4.6 passivation 50nm 轉換曲線……………………………………..54
圖4.7 passivation 50nm 輸出曲線..........................................................54
圖4.8 場板元件與傳統型受偏壓應力效應後的臨界電壓漂移曲線...57
圖4-9場板元件與傳統型受偏壓應力效應後gm degradation特性圖..58
圖4-10場板元件與傳統型再不同元件大小之崩潰電壓曲線..............59

表目錄
表4-1 RSDIS-TFT與傳統型之關鍵參數………………………………55

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