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研究生:黃郁為
研究生(外文):Yu-Wei Huang
論文名稱:以CMOS0.18-um設計之修改型式的管線式類比數位轉換器
論文名稱(外文):A modified pipelined ADC realization in 0.18-um CMOS technology
指導教授:王鴻猷
指導教授(外文):Hung-Yu Wang
學位類別:碩士
校院名稱:國立高雄應用科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:129
中文關鍵詞:管線式類比數位轉換器電流傳輸器米勒電容
外文關鍵詞:Pipelined ADCCurrent conveyorMiller capacitance
相關次數:
  • 被引用被引用:2
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快閃式類比轉換器(Flash analog-to-digital converter)是目前最快的一種架構,然而在提高解析度時,整體面積與消耗功率卻呈現大幅度的增加。因此,管線式類比數位轉換器(Pipelined analog-to-digital converter)相較於快閃式類比數位轉換器更適合發展高速與高解析度的架構。然而此種架構的效能往往取決於所使用的運算放大器,所以運算放大器的設計為管線式類比數位轉換器的設計重點。
此外,電流式主動元件的輸出輸入端因為具有電流或電壓的變數關係,在設計的彈性與簡便上比一般的運算放大器優越,可同時適用在電流模式與電壓模式的電路設計,也很快地成為高效能電路設計上常應用的主動元件。
本論文提出新型之第二代電流傳輸器實現之米勒電容取樣保持電路,此電路為管線式類比數位轉換器重要的區塊。本論文在取樣保持電路結合米勒電容取樣保持之技術,使其取樣開關與輸入訊號有關之電荷注入所造成的取樣誤差將會被抑制。本次所提出的新型取樣保持電路,其增加之運算放大器將由反向器取代;因此,將降低功率的消耗與晶片的面積。
整個晶片電路以台灣積體電路公司(TSMC) 0.18-μm 1P6M製程來實現,依據HSPICE的模擬結果,在輸入2MHz的正弦波時,訊號對雜訊及失真比(SNDR)為55.7dB,最大的積分非線性誤差(INL)與微分非線性誤差(DNL)分別為0.15LSB和0.1LSB。操作電壓為3.3V,其電路的功率消耗為16.7mW。晶片面積為0.35 mm2。
Among the analog-to-digital converter (ADC) architectures, flash ADC is the fastest one. Nonetheless, the power dissipation and the chip size will become exceedingly enormous as the resolution increased. The pipelined architecture is more suitable for applications of higher resolution and higher speed than flash architectures, due to its small size and low power dissipation. The accuracy of the pipelined ADC architecture based on operational amplifier is always depended on the operational amplifier performance. As a result, operational amplifier is the most critical circuit when designs a pipelined ADC.
Furthermore, current-mode active devices, which comprise voltage and current variables in their port relations of input and output, have been proved to possess favorable balance of operational flexibility and simplicity over their conventional operational amplifier counterparts. They are suitable to operate with signals in current-mode and in voltage-mode, rapidly gaining the acceptance of researches as building block in high-performance circuit designs.
The paper proposes a new sample-and-hold (S/H) circuit using a Miller-capacitance based on second-generation current conveyor (CCII) which is a main building block in pipelined analog-to-digital converter (ADC). With this technique, the sampling error resulting from input-dependent charge injection of the sampling switch is weakened. In the propose S/H circuit, operational amplifier is not used but an inverter. Therefore, low power and small chip area can be achieved.
The pipelined ADC is designed and implemented with TSMC 0.18-μm CMOS technology. With the HSPICE simulation result, a signal-to-noise-and-distortion ratio (SNDR) of 55.7 dB for a 2MHz sinusoidal input is achieved. The simulated results show the maximum INL and DNL are 0.15 LSB and 0.1 LSB, respectively. The power dissipates 16.7mw from a 3.3V power supply. The chip size of the ADC is about 0.35 mm2.
摘要 I
ABSTRACT II
致 謝 III
目 錄 IV
圖 目 錄 VI
表 目 錄 X
Chapter 1 緒論 1
1.1 前言 1
1.2 研究動機 1
1.3 論文架構 2
Chapter 2 類比數位轉換器架構概論 3
2.1 簡介 3
2.2 理想類比數位轉換器 3
2.3 類比數位轉換器特性參數 4
2.3.1 動態特性 4
2.3.2 靜態特性 8
2.4 類比數位轉換器架構介紹 13
2.4.1 快閃式類比數位轉換器(Flash ADC) 13
2.4.2 兩階段式類比數位轉換器(Two step ADC) 14
2.4.3 管線式類比數位轉換器(Pipeline ADC) 15
2.5 數位錯誤校正技術及1.5-bit管線式類比數位轉換器 18
Chapter 3 電流式系統相關介紹 24
3.1 簡介 24
3.2 等效Nullor模型 24
3.3 等效Mirror模型 27
3.4 電流傳輸器(CC)的特性 28
3.5 第二代電流傳輸器(CCII) 29
3.6 第二代電流傳輸器(CCII)之非理想模型 32
3.6.1 第二代電流傳輸器(CCII)之節點阻抗 33
3.7 第二代電流傳輸器(CCII)電路實現 35
Chapter 4 運算放大器之設計 38
4.1 簡介 38
4.2 運算放大器所需之規格 38
4.3 單級運算放大器 43
4.3.1 伸縮式(Telescopic)運算放大器 43
4.3.2 摺疊疊接式(Folded cascode)運算放大器 44
4.4 雙級式(Two stage)運算放大器 45
4.4.1 雙級式(Two stage)運算放大器之模擬結果 47
Chapter 5 管線式類比數位轉換器之分析與設計 49
5.1 簡介 49
5.2 開關式電容(Switch capacitor, SC)電路 49
5.2.1 MOS開關 49
5.2.2 通道電荷注入效應(Charge injection) 52
5.2.3 時脈饋入效應(Clock feed-through) 54
5.2.4 KT/C雜訊 55
5.2.5 靴帶式(Bootstrapped)開關 55
5.3 前端取樣及保持電路(Sample and hold circuit, S/H) 59
5.3.1 運算放大器實現之取樣保持電路 59
5.3.2 米勒電容取樣保持電路(Miller Capacitance S/H) 61
5.3.3 第二代電流傳輸器實現之米勒電容取樣保持電路 66
5.4 子類比數位轉換器(Sub-ADC) 71
5.4.1 比較器電路 71
5.4.2 1.5-bit子類比數位轉換器(Sub-ADC) 72
5.4.3 2-bit子類比數位轉換器 74
5.5 相乘式數位類比轉換器(Multiplying DAC, MDAC) 75
5.6 時脈產生器(Clock Generator) 79
5.7 延遲電路與數位錯誤校正電路 81
5.8 Pipelined ADC 模擬結果 85
5.9 結論 89
Chapter 6 佈局考量與測試考量 90
6.1 簡介 90
6.2 類比電路佈局技巧與考量 90
6.3 管線式類比數位轉換器之佈局 98
Chapter 7 結論 103
7.1 結論 103
7.2 未來改善 103
參考文獻 105
附錄一 109
量測考量 109
附錄二 123
10-bit管線式類比數位轉換器之Simulink behavior model 123
自  述 129
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