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研究生:莊薪樺
研究生(外文):Jhuang Sin-Hua
論文名稱:使用RAG法與改良型進位跳躍加法器實現FIR濾波器
論文名稱(外文):Implementation of FIR filter with Reduced Adder Graph and Modified Carry-Skip Adders
指導教授:王鴻猷
指導教授(外文):Wang Hung-Yu
學位類別:碩士
校院名稱:國立高雄應用科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:70
中文關鍵詞:FIR濾波器RAG演算法全加器32位元進位跳躍加法器
外文關鍵詞:FIR filterRAG algorithmFull adder32-bit carry skip adder
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  • 被引用被引用:1
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這篇論文完成了使用RAG法與改良型進位跳躍加法器實現FIR濾波器。在加法器裡我們使用低延遲的全加器、最佳化區塊以及低邏輯階層來完成高效能32位元加法器。我們將高效能加法器應用於pipeline retime line上,可以發現大部份的Finite Impulse Response(FIR)濾波器有所改善。因為使用Reduced Adder Graph (RAG)方法產生常數係數FIR濾波器電路,所需要的元件數比Canonic Signed Digit (CSD)表示法少,所以在這篇論文上我們使用RAG方法。在濾波器合成方面我們使用在1.8伏特的TSMC 0.18μm CMOS元件庫,以及FIR濾波器的硬體實現在FPGA。
This paper presents a FIR filter with reduced adder graph algorithm and modified carry-skip adders. We use low-delay full adders, optimized sizes for the skip blocks and reduced number of logic levels to achieve high performance result in the used 32-bit adder. We apply the high-performance adders in pipeline retime line to improve the performance of FIR filter. Because the reduced adder graph (RAG) method uses fewer components than the canonic signed digit (CSD) method for generating constant coefficient FIR filter topology, the RAG method is used in this paper. The designed filter is synthesized with TSMC 0.18μm CMOS cell library at 1.8V power supply. And the hardware of FIR filters is realized with FPGA.
摘 要 I
Abstract II
致 謝 III
目 錄 IV
圖目錄 V
Chapter 1 緒論 1
1.1 前言 1
1.2 研究動機 1
1.3 論文架構 2
Chapter 2 加法器 3
2.1 全加器 3
2.2 AOI/OAI閘 5
2.3 改良型進位跳躍加法器 6
2.4 結果與比較 12
Chapter 3 FIR濾波器原理與設計 14
3.1 濾波器係數 15
3.2 RAG法 17
3.2.1 F5濾波器設計使用RAG法 20
3.2.2 F6濾波器設計使用RAG法 20
3.2.3 F7濾波器設計使用RAG法 21
3.2.4 F8濾波器設計使用RAG法 21
3.2.5 F9濾波器設計使用RAG法 22
3.3 F5-F9的CSD表示法 29
3.4 結果與比較 30
3.4.1 RAG與CSD比較 30
3.4.2 整體效能比較 31
Chapter 4 FIR濾波器模擬與實體測試 32
4.1 ChipScope 32
4.2 測試結果整理 33
4.2.1 F5濾波器測試 33
4.2.2 F6濾波器測試 34
4.2.3 F7濾波器測試 35
4.2.4 F8濾波器測試 36
4.2.5 F9濾波器測試 37
Chapter 5 結論與未來展望 38
參考文獻 39
附錄一 標準符號數位(CSD)表示法基本介紹 41
附錄二 RAG產生器使用說明 43
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