臺灣博碩士論文加值系統

近年來，由於電池供電電子系統的蓬勃發展，為了此類產品能夠正確的運作及使電池供電時間增長，電源電路必需具備體積小、低電壓、高效率與低功率消耗等特性，才能提升市場的競爭力。
本論文包含了帶隙參考電壓電路、轉阻運算放大器以及低壓降穩壓器三個主題。第一個部份首先討論在電源IC中，佔有相當重要性的參考電壓電路，提出新型的微功率低電壓帶隙參考電壓電路，實現了一個不易受溫度影響的參考電壓穩積體電路。第二部份，為了改善電壓模式設計的放大器不適合應用在高頻訊號處理，提出一個依據電流回授放大器的電路特性使用電流處理技術設計運算轉阻放大器(Operational Transresistance Amplifier, OTRA)，以此元件所設計的電路具有固定頻寬的特性，且具有較佳的雜散免疫力。論文的第三部份，討論電源電路系統所需要的低壓降穩壓器(Low Dropout Regulator, LDO)並完成電路之設計與實現，低壓降穩壓器在近年來廣泛地應用在各式電子產品上，由於這些電路設計上是可以提供精確的輸出電壓，所以低壓降穩壓電路的設計重點著重於降低雜訊、降低功率消耗、降低响應時間與提升效率等特性上。此低壓降穩壓器由誤差放大器、補償電路以及電源開關電晶體(Power MOS)與分壓電阻所組合而成。
此晶片是使用台積電0.35μm 2P4M互補式金氧半製程來實現，轉換器之效率最高可達85%，而其他相關的設計原理與性能參數將會在接下來的章節中描述。

In recent years, battery powered electronic devices are in great demand of consumer markets. To work properly, the devices must drain power from battery, which contains only limited energy. As a result, the trend of smart power supply is focused on implementation of power converter with high-efficiency, low-voltage, and low-power consumption.
Three topics are included in this thesis: bandgap reference circuit, operational transresistance amplifier (OTRA) and low dropout regulator (LDO). The bandgap reference circuit will be discussed first. Its output voltage is constant and independent of temperature variation. The proposed OTRA features the advantages of high frequency. The circuit so that its characteristics with fixed bandwidth and has better noise immunity. Finally, the third part of this thesis, aim at the design and implementation of the LDO which is widely used in power electronic systems. The design efforts are focused on reduction the output noise, power consumption, response time and increasing the efficiency of the regulator.
The circuits are designed and fabricated in a TSMC 0.35-µm CMOS process. Maximum efficiency of the converter is 85%. The other related design principles and performance parameter will describe in the next chapter.

中文摘要 i
英文摘要 ii
誌 謝 iii
目 錄 iv
圖目錄 vii
表目錄 xi
第一章 緒論 1
1.1 相關研究與發展現況 1
1.2 研究動機與目的 2
1.3 IC設計流程 4
1.4 論文內容架構 5
第二章 帶隙參考電壓電路概論 6
2.1 不受溫度係數影響的參考電壓電路 6
2.1.1 正溫度係數電壓 7
2.1.2 負溫度係數電壓 8
2.1.3 正與負溫度係數間的補償關係 9
2.1.4 雙極性電晶體在CMOS製程技術中的相容性 9
2.2 帶隙參考電壓電路之設計原理 10
2.2.1 曲率校正 12
2.3 帶隙參考電壓電路製作 13
2.3.1 運算放大器與偏壓電路 14
2.3.2 傳統型帶隙參考電壓電路 16
2.3.3 微功率低電壓型帶隙參考電路 17
2.4 模擬結果 18
第三章 運算轉阻放大器 21
3.1 運算轉阻放大器設計原理 21
3.1.1 非反相放大器 23
3.1.2 反相放大器 23
3.1.3 積分與微分器 24
3.1.4 寄生電容的影響 25
3.2 運算放大器與各應用電路之模擬結果 25
第四章 電壓模式之低壓降穩壓器 30
4.1 電壓式低壓降穩壓器(LDO) 30
4.2 低壓降穩壓器基本架構概述 30
4.3 低壓降穩壓器基本性能參數定義 31
4.3.1 輸出電壓差(Dropout voltage) 31
4.3.2 線性調節率(Line regulation) 32
4.3.3 負載調節率(Load regulation) 34
4.3.4 接地電流(Ground current) 34
4.3.5 轉換效率(Efficiency) 35
4.3.6 迴授方式及電路穩定性(Feedback and Loop Stability) 35
4.3.7 低壓降穩壓器的補償 36
4.3.8 輸出電壓準確率(Output accuracy) 37
4.3.9 暫態響應(Transient response) 39
4.4 低壓降穩壓器電路製作 40
4.4.1 誤差放大電路的電路分析 41
4.4.2 補償電路 42
4.4.3 LDO完整電路的電壓增益分析 42
4.4.4 LDO完整電路的輸出與輸入阻抗分析 43
4.5 模擬結果 44
第五章 電路佈局與量測結果 51
5.1 微功率低電壓型帶隙參考電壓電路整體佈局 52
5.1.1 量測環境 53
5.1.2 測量結果 55
5.2 運算轉阻放大器電路整體佈局 57
5.3 電壓模式之低壓降穩壓器電路整體佈局 57
5.3.1 量測環境 58
5.3.2 測量結果 60
第六章 結論與未來展望 62
6.1 結論 62
6.2 未來展望 62
參考文獻 63

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