低溫多晶矽薄膜電晶體（Low temperature poly silicon thin film transistor, LTPS-TFT）是近年來應用於液晶平面顯示器中的一項重要技術。在元件可靠性上正偏壓溫度不穩定性（Positive bias temperature instability, PBTI）應力又顯示出比熱載子應力（Hot carrier stress, HCS）所造成元件性能更是嚴重劣化。在此論文中，所採用的實驗樣本為固態連續波綠光雷射結晶（Continuous-wave laser crystallization, CLC）技術所製成之多晶矽薄膜電晶體。其優點乃在於能克服超大型面板在使用多晶矽薄膜電晶體元件時，難以控制執行脈衝波間之阻礙，且隨著連續波雷射能量的提高，其通道結晶性，通常也相對地增加。此多晶矽薄膜電晶體利用增強型電漿化學氣相沉積（Plasma enhanced chemical vapor deposition, PECVD）技術成長TEOS-SiO2（四乙氧基矽烷，Si(OC2H5)4）薄膜100nm厚度作為閘極端氧化層。
本篇論文中，主要探討在施加高垂直電壓應力和高溫度衝擊下，瞭解多晶矽薄膜電晶體元件性能之劣化或缺陷形成。本實驗設定的條件為，溫度調變範圍自25 ℃變化至150 ℃，其閘極端施加的電壓為18V及20V，汲極端和源極端為接地。從實驗結果得知，連續波雷射退火多晶矽薄膜電晶體在高垂直電壓應力和高溫度應力條件下，閘極氧化層與多晶矽通道間的介面狀態（Interface state）所造成的劣化情形，指向是矽-氫鍵斷裂或介面缺陷狀態，造成元件性能劣化乃是主因。而隨著退火能量的提高，發現元件劣化的程度有些許減緩。

Recently, low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) have been the trend of active matrix display driving circuitry. These devices unavoidably show more serious degradation of device performance in BTI (BTI) stress than in hot-carrier stress (HCS). In this study, the proposed TFT channel was fabricated with continuous-wave (CW) green laser-crystallization (CLC) conquering the barrier of the hardly controlled pulse-to-pulse repeatability (PPR) and implementing the possibility of large-area panel of poly-Si TFT, and the degree of crystallization increases of channel layer by CW laser. The gate dielectric was deposited of TEOS-SiO2 with a 100-nm thickness by plasma enhanced chemical vapor deposition (PECVD).
The defect generation of CLC poly-Si TFT under high gate-voltage stress and temperature impact was firstly investigated. The PBTI stress was performed at the temperature range varied from 25 ℃ to 125 ℃ and the stress gate voltages were 18V and 20V with the source and drain grounded. From the experimental results, the degradation mechanism of device performance in CLC poly-Si TFT under two stress conditions and various laser anneals was chiefly caused by the surface interface between gate oxide and channel poly-Si, especially dissolving Si-H+ bonds or producing the interface states. Furthermore, since the laser anneal energy was raised, the PBTI degradation was slightly improved.

中文摘要 i
英文摘要 ii
誌 謝 iii
目 錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究動機與背景 1
1.2 平面顯示器簡介 2
1.3 論文架構 3
第二章 半導體元件概論 4
2.1 半導體的能隙與載子濃度 4
2.1.1 半導體的能帶與能隙 5
2.1.2 熱平衡狀態下的載子濃度 7
2.1.3 P-N接面 10
2.1.4 p-n接面崩潰 16
2.1.4.1 齊納崩潰 16
2.1.4.2 雪增崩潰 17
2.2 金屬氧化物半導體場效應電晶體 19
2.2.1 理想MOS元件 20
2.2.1.1 理想MOS電容 20
3.2.1.2 臨界電壓 22
2.2.2 長通道MOSFET 23
2.2.2.1 基本特性操作 23
2.2.2.2 轉換特性 26
2.2.2.3 次臨界特性 27
2.2.2.4 基板偏壓效應 28
2.2.2.5 遷移率退化 29
2.3 氧化層缺陷之型態 30
2.3.1 介面缺陷電荷 32
2.3.2 氧化層固定電荷 33
2.3.4 可移動離子電荷 35
2.3.5 外表面電荷 36
2.4 氧化層的電流傳導機制 36
2.4.1 直接穿隧 37
2.4.2 F-N穿隧 38
2.4.3 蕭特基發射/熱發射 40
2.4.4 法蘭克-普爾效應 41
2.4.5 空間電荷限制電流 43
第三章 多晶矽薄膜電晶體 44
3.1 薄膜電晶體元件 44
3.1.1 多晶矽薄膜製程 45
3.1.1.1 固相結晶法 45
3.1.1.2 金屬誘發結晶法 45
3.1.1.3 金屬誘發側向結晶法 46
3.1.1.4 準分子雷射退火法 46
3.1.1.5 固態連續波雷射結晶法 48
3.2 電性特性分析 49
3.2.1 臨界電壓 49
3.2.2 次臨界擺幅 50
3.2.3 場效遷移率 50
3.2.4 開關電流比 51
3.2.5 通道電阻與寄生電阻 51
3.3 偏壓溫度不穩定性 52
第四章 實驗結果與分析 57
4.1 元件結構 57
4.2 儀器設備 59
4.3 正偏壓溫度不穩定性對薄膜電晶體穩定的影響 63
4.3.1 爐管活化多晶矽薄膜電晶體之分析 63
4.3.2 雷射活化多晶矽薄膜電晶體之分析 71
4.3.3 不同活化方式多晶矽薄膜電晶體之比較 74
第五章 結論 76
參考文獻 77

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