臺灣博碩士論文加值系統

低溫多晶矽薄膜電晶體（Low temperature poly silicon thin film transistor, LTPS-TFT）是近年來應用於液晶平面顯示器中的一項重要技術。在元件可靠性上正偏壓溫度不穩定性（Positive bias temperature instability, PBTI）應力又顯示出比熱載子應力（Hot carrier stress, HCS）所造成元件性能更是嚴重劣化。在此論文中，所採用的實驗樣本為固態連續波綠光雷射結晶（Continuous-wave laser crystallization, CLC）技術所製成之多晶矽薄膜電晶體。其優點乃在於能克服超大型面板在使用多晶矽薄膜電晶體元件時，難以控制執行脈衝波間之阻礙，且隨著連續波雷射能量的提高，其通道結晶性，通常也相對地增加。此多晶矽薄膜電晶體利用增強型電漿化學氣相沉積（Plasma enhanced chemical vapor deposition, PECVD）技術成長TEOS-SiO2（四乙氧基矽烷，Si(OC2H5)4）薄膜100nm厚度作為閘極端氧化層。
本篇論文中，主要探討在施加高垂直電壓應力和高溫度衝擊下，瞭解多晶矽薄膜電晶體元件性能之劣化或缺陷形成。本實驗設定的條件為，溫度調變範圍自25 ℃變化至150 ℃，其閘極端施加的電壓為18V及20V，汲極端和源極端為接地。從實驗結果得知，連續波雷射退火多晶矽薄膜電晶體在高垂直電壓應力和高溫度應力條件下，閘極氧化層與多晶矽通道間的介面狀態（Interface state）所造成的劣化情形，指向是矽-氫鍵斷裂或介面缺陷狀態，造成元件性能劣化乃是主因。而隨著退火能量的提高，發現元件劣化的程度有些許減緩。

Recently, low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) have been the trend of active matrix display driving circuitry. These devices unavoidably show more serious degradation of device performance in BTI (BTI) stress than in hot-carrier stress (HCS). In this study, the proposed TFT channel was fabricated with continuous-wave (CW) green laser-crystallization (CLC) conquering the barrier of the hardly controlled pulse-to-pulse repeatability (PPR) and implementing the possibility of large-area panel of poly-Si TFT, and the degree of crystallization increases of channel layer by CW laser. The gate dielectric was deposited of TEOS-SiO2 with a 100-nm thickness by plasma enhanced chemical vapor deposition (PECVD).
The defect generation of CLC poly-Si TFT under high gate-voltage stress and temperature impact was firstly investigated. The PBTI stress was performed at the temperature range varied from 25 ℃ to 125 ℃ and the stress gate voltages were 18V and 20V with the source and drain grounded. From the experimental results, the degradation mechanism of device performance in CLC poly-Si TFT under two stress conditions and various laser anneals was chiefly caused by the surface interface between gate oxide and channel poly-Si, especially dissolving Si-H+ bonds or producing the interface states. Furthermore, since the laser anneal energy was raised, the PBTI degradation was slightly improved.

中文摘要 i
英文摘要 ii
誌 謝 iii
目 錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究動機與背景 1
1.2 平面顯示器簡介 2
1.3 論文架構 3
第二章 半導體元件概論 4
2.1 半導體的能隙與載子濃度 4
2.1.1 半導體的能帶與能隙 5
2.1.2 熱平衡狀態下的載子濃度 7
2.1.3 P-N接面 10
2.1.4 p-n接面崩潰 16
2.1.4.1 齊納崩潰 16
2.1.4.2 雪增崩潰 17
2.2 金屬氧化物半導體場效應電晶體 19
2.2.1 理想MOS元件 20
2.2.1.1 理想MOS電容 20
3.2.1.2 臨界電壓 22
2.2.2 長通道MOSFET 23
2.2.2.1 基本特性操作 23
2.2.2.2 轉換特性 26
2.2.2.3 次臨界特性 27
2.2.2.4 基板偏壓效應 28
2.2.2.5 遷移率退化 29
2.3 氧化層缺陷之型態 30
2.3.1 介面缺陷電荷 32
2.3.2 氧化層固定電荷 33
2.3.4 可移動離子電荷 35
2.3.5 外表面電荷 36
2.4 氧化層的電流傳導機制 36
2.4.1 直接穿隧 37
2.4.2 F-N穿隧 38
2.4.3 蕭特基發射/熱發射 40
2.4.4 法蘭克-普爾效應 41
2.4.5 空間電荷限制電流 43
第三章 多晶矽薄膜電晶體 44
3.1 薄膜電晶體元件 44
3.1.1 多晶矽薄膜製程 45
3.1.1.1 固相結晶法 45
3.1.1.2 金屬誘發結晶法 45
3.1.1.3 金屬誘發側向結晶法 46
3.1.1.4 準分子雷射退火法 46
3.1.1.5 固態連續波雷射結晶法 48
3.2 電性特性分析 49
3.2.1 臨界電壓 49
3.2.2 次臨界擺幅 50
3.2.3 場效遷移率 50
3.2.4 開關電流比 51
3.2.5 通道電阻與寄生電阻 51
3.3 偏壓溫度不穩定性 52
第四章 實驗結果與分析 57
4.1 元件結構 57
4.2 儀器設備 59
4.3 正偏壓溫度不穩定性對薄膜電晶體穩定的影響 63
4.3.1 爐管活化多晶矽薄膜電晶體之分析 63
4.3.2 雷射活化多晶矽薄膜電晶體之分析 71
4.3.3 不同活化方式多晶矽薄膜電晶體之比較 74
第五章 結論 76
參考文獻 77

1. 王木俊、劉傳璽，薄膜電晶體液晶顯示器：原理與實務，新文京開發出版社，民國97年。
2. 顧鴻壽，光電液晶平面顯示器技術基礎及應用，新文京開發出版社，民國93年。
3. 陳志強，LTPS低溫複晶矽顯示器技術，全華科技，民國93年。
4. 田民波，平面顯示器之技術發展，五南出版社，民國97年。
5. 劉傳璽、陳進來，半導體元件物理與製程-理論與實務，五南圖書出版社，民國95年。
6. Hong Xiao原著；羅正忠、張鼎張譯，半導體製程技術導論，台灣培生教育出版，民國91年。
7. Ben G. Streeetman, Sanjay Banerjee原著；吳孟奇等譯，東華書局，民國90年。
8. L. W. Snyman, M. du Plessis, E. Seevinck, and H. Aharoni, “An efficient low voltage, high frequency silicon CMOS light emitting device and electro-optical interface,” IEEE Electron Device Lett., Vol. 20, 1999, pp. 614-617.
9. A. G. Ghynoweth and K. G. McKay, “Photon emission from avalanche breakdown in silicon,” Phys. Rev., Vol. 102, 1956, pp. 369-376.
10. G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-k dielectrics reliability issues,” IEEE Device and Materials Reliability, Vol. 5, 2005, pp.5-19.
11. V. Martin Agostinelli, Greg M. Yeric, and Al F. Tasch, “Universal MOSFET hole mobility degradation models for circuit simulation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, 1999, pp. 439-445.
12. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universal mobility of inversion layer mobility in Si MOSFETs: Part II—Effect of surface orientation,” IEEE Trans. Electron Devices, Vol. 41, 1994, pp. 2363-2368.
13. B. E. Deal, “Standardized terminology for oxide charges associated with thermally oxidized silicon,” IEEE Trans. on Electron Devices, Vol. 27, 1980, pp. 606-608.
14. D. M. Fleetwood and N. S. Saks, “Oxide, interface, and border traps in thermal, N2O, and N2O-nitrided oxides,” J. Appl. Phys., Vol. 79, 1996, pp. 1583-1594.
15. J. R. Schwank, M. R. Shaneyfelt, D. M. Fleetwood, J. A. Felix, P. E. Dodd, P. Paillet, and V. F. Cavrois, “Radiation Effects in MOS Oxides,” IEEE Trans. on Nuclear Science, Vol. 55, 2008, pp. 833-853.
16. T. J. Russell, C. L. Wilson, and M. Gaitan, “Determination of the spatial variation of interface trapped charge using short-channel MOSFET's,” IEEE Trans. Electron Devices, Vol. 30, 1983, pp. 1662-1671.
17. S. C. Witczak, K. F. Galloway, R. D. Schrimpf, J. L. Titus, J. R. Brews and G. Prevost, “The determination of Si-SiO2 interface trap density in irradiated four-terminal VDMOSFETs using charge pumping,” IEEE Trans. on Nuclear Science, Vol. 43, 1996, pp.2558-2564.
18. S. Masui, T. Nakajima, K. Kawamura, T. Yano, I. Hamaguchi, K. Kajiyama, and M. Tachimori, “Evaluation of fixed oxide charge and oxide-silicon interface trap densities in low-dose and high-dose SIMOX wafers,” IEEE International SOI Conference, 1994, pp. 83-84.
19. F. T. Brady, S. S. Li, and D. E. Burk, “Determination of the fixed oxide charge and interface trap densities for buried oxide layers formed by oxygen implantation,” Appl. Phys. Lett., Vol. 52, 1988, pp. 886-888.
20. N. S. Saks and D. B. Brown, “Observation of H+ motion during interface trap formation, “ IEEE Trans. on Nuclear Science, Vol. 37, 1990, pp. 1624-1631.
21. A. Goetzberger, E. Klausmann and M. J. Schulz, “Interface states on semiconductor/insulator interface,” Solid State Science, 1976, pp. 1-43.
22. G. Declerck, “Characterization of surface states at the Si-SiO2 interface,” in Nondestructive Evaluation of Semiconductor Materials and Devices (J. N. Zemel, ed) Plenum Press, New York, 1979, pp. 105-148.
23. W. C. Johnson, “Mechanisms of Charge Buildup in MOS Insulators,” IEEE Trans. on Nuclear Science, Vol. 22, 1975, pp. 2144-2150.
24. N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices,” IEEE Trans. Electron Devices, Vol. 46, 1999, pp. 1464-1471.
25. K. N. Yang, H. T. Huang, M. C. Chang, C. M. Chu, Y. S. Chen, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p+ poly-gate pMOSFETs with ultrathin gate oxides, “ IEEE Trans. Electron Devices, Vol. 47, 2000, pp. 2161-2166.
26. G. Chakraborty, S. Chattopadhyay, C. K. Sarkar, and C. Pramanik, “Tunneling current at the interface of silicon and silicon dioxide partly embedded with silicon nanocrystals in metal oxide semiconductor structures” J. Appl. Phys.,Vol. 101, 2007.
27. Y. Tang, J. Chen, C. Chang, D. Liu, S. Haddad, Y. Sun, A. Wang, M. Ramskey, M. Kwong, H. Kinoshita, W. H. Chan, and J. Lien, “Different dependence of band-to-band and Fowler-Nordheim tunneling on source doping concentration of an n-MOSFET,” IEEE Electron Device Lett., Vol. 17, 1996, pp. 525-527.
28. R. Jhaveri, V. Nagavarapu, and J. C. Woo, “Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications,” IEEE Trans. Electron Devices, Vol. 56, 2009, pp. 93-99.
29. R. A. Vega, “Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier lowering,” IEEE Trans. Electron Devices, Vol. 53, 2006, pp. 1593-1600.
30. J. Furlan, Z. Gorup, A. Levstek, and S. Amon, “Thermally assisted tunneling and the Poole–Frenkel effect in homogenous a-Si,” J. Appl. Phys., Vol. 94, 2003, pp. 7604-7610.
31. R. Ajjel, M. A. Zaidi , S. Alaya, G. Bremond, G. Guillot, J. C. Bourgoin, “Poole-Frenkel effect assisted emission from deep donor level in chromium doped GaP,” Appl. Phys. Lett., Vol. 72, 1998, pp. 302-304.
32. S. C. Jain, W. Geens, A. Mehra, V. Kumar, T. Aernouts, J. Poortmans, R. Mertens, Willander M., “Injection-and space charge limited-currents in doped conducting organic materials,” J. Appl. Phys., Vol. 89, 2001, pp. 3804-3810.
33. M. Shintaro, Y. Motoji, T. Nobuaki, S. Kazuhiko, S. Keiichi, M. Yoshiteru, K. Kunio, T. Akira, O. Kenji, “Huge magnetoresistive effects using space charge limited current in ZnO/SiO2 system,” Appl. Phys. Lett., Vol. 91, 2007.
34. 田民波，薄膜技術與薄膜材料，五南圖書出版社，民國96年。
35. D. D. Malinovska, O. Angelov, M. S. Vassileva, V. Grigorov, J. C. Pivin, “Polycrystalline Si films on glass substrates prepared by metal induced crystallization,” 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, Vol. 3, 2004, pp. 530-534.
36. C. Y. Yuen, M. C. Poon, M. Chan, W. Y. Chan, and M. Qin, “TFT fabrication on MILC polysilicon film with pulsed rapid thermal annealing,” Electron Devices Meeting, 2000, pp. 72-75.
37. N. Kubo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characterization of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, 1994, Vol. 41, pp. 1876-1879.
38. T. C. Cheng, W. C. Chang, K. F. Yarn, C. F. Lo, J. K. Kuo, “Optimization of excimer laser annealing on low temperature polysilicon for thin film transistor applications,” 8th International Conference on Solid-State and Integrated Circuit Technology, 2006, pp. 266-268.
39. G. K. Giust and T. W. Sigmon,, “High-performance thin-film transistors fabricated using excimer laser processing and grain engineering,” IEEE Trans. Electron Devices, Vol. 45, 1998, pp. 925-932.
40. Y. T. Lin, C. Chen, J. M. Shieh, and C. L. Pan, “Stability of continuous-wave laser-crystallized epilike silicon transistors,” Appl. Phys. Lett., Vol. 90, 2007, pp.073508.
41. S. Luan and G. W. Necudeck, “An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin transistors,” J. Appl. Phys., 1992, pp.766-772.
42. N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Irnai, and T. Horiuchi, “The impact of bias temperature instability for direct-tunnelingultra-thin gate oxide on MOSFET scaling,” Symposium on VLSI Technology, 1999, pp. 73-74.
43. A. Khamesra, R. Lal , J. Vasi, A. Kurriar K. P., and J. K. O. Sin, “Device degradation of n-channel poly-Si TFTs due to high field, hot carrier, and radiation stressing,” in Proc. IPFA, 2001, pp. 258-262.
44. N. Bhat, M. Cao, and K. C. Saraswat, “Bias temperature instability in hydrogenated thin-film transistors,” IEEE Trans. Electron Devices, Vol. 44, 1997, pp.1102-1108.
45. M. W. Ma, C. Y. Chen, W. C. Wu, C. J. Su, K. H. Kao, T. S. Chao, and T. F. Lei, “Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: pbti, nbti, and hot-carrier stress,” IEEE Trans. Electron Devices, Vol. 55, 2008, pp.1153-1160.
46. C. Y. Chen, M. W. Ma, W. C. Chen, H. Y. Lin, K. L. Yeh, S. D. Wang, and T. F. Lei, “Analysis of negative bias temperature instability in body-tied low-temperature polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., Vol. 29, 2008, pp.165-167.
47. M. W. Ma, C. Y. Chen, C. J. Su, W. C. Wu, Y. H. Wu, K. H. Kao, T. S. Chao, and T. F. Lei, “ Characteristics of pbti and hot carrier stress for LTPS-TFT with high-k gate dielectric,” IEEE Electron Device Lett., Vol. 29, 2008, pp.171-173.
48. C. Y. Chen, J. W. Lee, P. H. Lee, W. C. Chen, H. Y. Lin, K. L. Yeh, M. W. Ma, S. D. Wang, and T. F. Lei, “A reliability model for low-temperature polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., Vol. 28, 2007, pp. 392-394.
49. 林鈺庭，連續波固態綠光雷射退火之面板型類磊晶矽電晶體，交通大學，材料科學與工程系所博士論文，民國96年。