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研究生:王明凱
研究生(外文):Ming-Kai Wang
論文名稱:低電壓內嵌式非揮發性記憶體元件之設計
論文名稱(外文):Design of Low-Voltage Embedded Non-Volatile Memory Devices
指導教授:林泓均
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:119
中文關鍵詞:低電壓內嵌式非揮發性記憶體
外文關鍵詞:Low-VoltageEmbeddedNon-Volatile Memory Devices
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近年來內嵌式的記憶體架構,已被廣泛的應用在各種不同的系統上,而在密度、功率消耗以及記憶體容量上,必須不斷的提高效能。而內嵌式的記憶體系統,設計重點在於是否能跟記憶體系統以外的電路,整合在相同的製程上。如果能使用相同的製程,而又不需要增加額外的光罩,不論在設計或是製造上,都會節省相當多的時間與成本。
本論文的研究目標是參考文獻中所使用的一般CMOS製程的Single-Poly EEPROM記憶體結構與觀念,除了繼續探討此結構在不同製程下的表現,並透過設計的新型結構OTP(One Time Programming)非揮發性記憶體元件,也搭配T-CAD ISE 10.0模擬平台環境中Sentaurus Structure Editor(Sentaurus SE)這套元件結構模擬工具與HSPICE電性模擬工具等,對此元件做詳盡的介紹與動作原理分析,同時透過UMC 90nm製程的下線實作晶片及量測,運用各種MOS電晶體所設計的記憶體元件做OTP測試,以期找出適合的非揮發性記憶體操作條件。
In recent years, the embedded storage devices have been extensively applied to different systems. The density, power consumption and capacity are continually improved to enhance the performance. The key issue of embedded memory is to integrate the other circuit with the memory array in the same process technology without extra masks. That would reduce significant development time and fabrication cost.
The goal of this thesis is to investigate the memory structures and design concept of well-known single-poly EEPROM using the standard CMOS technology. In addition to continuously study the performance of the same structures in different process technology, the novel OTP(One Time Programming)non-volatile memory device was designed with the assistance of the simulation tools - T-CAD ISE 10.0 Sentaurus Structure Editor(Sentaurus SE)and HSPICE. The detailed introduction and analysis of its operation principles were also presented. Using UMC 90nm technology, many memory devices with various MOS transistors were fabricated and measured in order to find the appropriate OTP non-volatile memory operation conditions.
誌 謝 i
中文摘要 ii
Abstract iii
目 錄 iv
表 目 錄 vi
圖 目 錄 vii
第一章 序 論 - 1 -
第一節 前 言 - 1 -
一、動態隨機存取記憶體(DRAM) - 3 -
二、靜態隨機存取記憶體(SRAM) - 4 -
三、罩幕式唯讀記憶體(Mask ROM) - 5 -
四、可程式唯讀記憶體(Programmable ROM) - 7 -
五、可抹除且可程式之唯讀記憶體(Erasable Programmable ROM) - 7 -
六、可電性抹除且可程式之唯讀記憶體(Electrically EPROM) - 9 -
第二節 快閃記憶體簡介 - 11 -
第三節 通道載子注入現象 - 14 -
一、快閃記憶體的物理機制 - 14 -
二、熱載子效應(Hot Carries Effect) - 15 -
三、冷載子效應(Cold Carries Effect) - 20 -
第四節 論文內容簡介 - 25 -

第二章 嵌入式非揮發性記憶體元件結構之研究 - 26 -
第一節 SONOS記憶體元件結構原理分析 - 27 -
一、SONOS元件結構原理分析 - 28 -
二、元件寫入機制原理(Program) - 30 -
三、元件抹除機制原理(Erase) - 30 -
四、元件臨界電壓值(Threshold Voltage) - 34 -
第二節 EEPROM記憶體元件結構原理分析 - 36 -
一、EEPROM元件結構原理分析 - 36 -
二、元件寫入機制原理(Program) - 40 -
三、元件抹除機制原理(Erase) - 42 -
第三節 MTP記憶體元件結構原理分析 - 43 -
一、MTP元件結構原理分析 - 43 -
二、元件寫入機制原理(Program) - 46 -
三、元件抹除機制原理(Erase) - 49 -
四、電荷存儲層(CSN)寫入狀態分析 - 51 -

第三章 低電壓內嵌式非揮發性記憶體元件設計 - 55 -
第一節 SONOS記憶體元件設計與分析 - 57 -
一、SONOS元件結構設計與製程參數設定 - 57 -
二、模擬結果分析 - 61 -
第二節 EEPROM記憶體元件設計與分析 - 68 -
一、EEPROM元件結構設計與製程參數設定 - 69 -
二、模擬結果分析 - 73 -
第三節 OTP記憶體元件設計與分析 - 77 -
一、OTP元件結構設計與製程參數設定 - 78 -
二、模擬結果分析 - 82 -

第四章 元件量測結果與討論 - 87 -
第一節 元件量測環境 - 88 -
第二節 EEPROM元件量測結果與分析 - 89 -
一、TSMC 0.35μm製程之記憶體元件量測結果 - 90 -
二、TSMC 0.25μm製程之記憶體元件量測結果 - 94 -
三、TSMC 0.18μm製程之記憶體元件量測結果 - 98 -
第三節 OTP元件量測結果與分析 - 103 -
一、UMC 90nm製程之OTP記憶體測試元件列表 - 104 -
二、UMC 90nm OTP記憶體測試元件寫入狀態時量測結果 - 108 -

第五章 未來規劃與結論 - 115 -
第六章 參考文獻 - 117 -
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