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研究生:吳海明
研究生(外文):Hai-Ming Wu
論文名稱:切換式電容參考電壓與PMOS電荷幫浦電路設計
論文名稱(外文):Design of Switched-Capacitor Voltage Reference and PMOS Charge Pump Circuits
指導教授:林泓均
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:70
中文關鍵詞:參考電壓切換式電容電荷幫浦
外文關鍵詞:Voltage referenceSwitched-capacitorCharge pump
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非揮發記憶體需要有較高電壓來執行寫入和抹除記憶體內部的資料,所以運用高電壓調節器來提供一個穩定的高電壓,對於非揮發記憶體而言是非常重要的課題。欲達到此目的必須有一個可產生高於電源電壓的幫浦電路,以及一穩定的參考電壓電路,由於此電壓調節器欲運用於內嵌式非揮發記憶體,都必須運用一般標準CMOS製程來完成,因此本論文的研究重點有二:一為PMOS電荷幫浦電路的改良,二為切換電容式參考電壓電路的研究,兩者皆需使用一般標準CMOS製程來設計。
  在電荷幫浦電路中,我們提出了一個2倍壓的時脈產生電路來控制開關電晶體的閘極,以改善Racapé電荷幫浦中開關電晶體的壓差過低的缺點,如此可以使得操作在低供應電壓和較高負載電流下的Racapé電荷幫浦也有很高的輸出電壓。我們採用TSMC 0.18μm製程來驗証我們所提出的電路架構,當操作在1.8V的電源電壓且無負載下,兩級的改良式Racapé電荷幫浦電路,其量測的輸出電壓可高達5.16 V。
  切換電容式的參考電壓是利用兩個非重疊時脈來控制開關電容,並且利用二個不同電流流經操作在次臨界區的二極式的NMOS電晶體以取出穩定的參考電壓。此種切換電容式的參考電壓電路主要的優點是適合操作在極低的電源電壓、易於產生低於1V以下的參考電壓,未使用BJT元件,所以佔的面積極小。
Much higher than supply voltages are required for program and erase of non-volatile memories, high voltage regulator circuits are usually used to have a stable high voltage. For embedded non-volatile memories, the regulator requires a stable reference voltage circuit and a charge pump to generate a voltage higher than supply voltage. The challenge is both of them have to be designed using the standard CMOS technology for the embedded system. This thesis is focused on two circuit blocks. The first block is to modify driving capability of Racapé’s charge pump circuit. The second one is to design a voltage reference using switched-capacitor approach.
A simple two-phase clock scheme to enhance the driving capability of Racapé’s charge pump circuit for low-voltage applications is proposed in this thesis. The proposed PMOS charge pump was simulated and verified by using TSMC 0.18μm CMOS technology. The measured results show that, under no load current, the output voltage of the proposed charge pump is about 5.16V at a supply voltage of 1.8V and a frequency of 10MHz.
  A switched-capacitor voltage reference circuit that controlled by two out-of-phase clocks is presented. The proposed reference circuit can generate a voltage using a sub-threshold diode-connected NMOS transistor that is switched between two different bias conditions. The main features of the proposed reference circuit include generating a sub-1V voltage reference, no parasitic BJT devices, small chip area, and operated at low supply voltage.
誌謝 i
摘要 ii
Abstract iii
目錄 iv
表目錄 v
圖目錄 vi

第一章 序論 1
第一節 發展現況與相關研究 1
第二節 論文內容簡介 6

第二章 切換式電容電荷幫浦調節器設計原理 7
第一節 切換式電容電路的基本操作原理 7
第二節 切換式電容電路基本應用 9
第三節 電荷幫浦電路基本原理 11
第四節 參考電壓產生電路 15
第五節 切換式電容電荷幫浦調節器 17
第六節 切換式電容CMOS參考壓電路 20

第三章 切換式電容參考電壓電路設計 22
第一節 切換式電容參考電壓系統架構 22
第二節 改良式傳統偏壓電路 23
第三節 以二極體方式連接的NMOS的溫度係數 26
第四節 非重疊時脈信號產生器 27
第五節 轉導放大器 28
第六節 切換式電容參考電壓電路 32
第七節 對製程變異的敏感度 36
第八節 切換式電容參考電壓電路模擬與量測結果 36

第四章 二相位PMOS電荷幫浦電路設計 53
第一節 二相位PMOS電荷幫浦電路 53
第二節 二相位PMOS電荷幫浦電路模擬與量測結果 56

第五章 結論與未來工作 67
參考文獻 68
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