近年來，由於環保意識抬頭，無鉛銲錫廣泛地應用於電子產品與電路板的接合上。相較於傳統錫鉛銲錫，無鉛銲錫較硬且脆的特性，尤其在動態荷載下極易發生破裂，致使電子產品承受動態荷載，其可靠度面臨更嚴苛的挑戰。在半導體封裝業中，電子產品封裝之使用壽命為最主要考量，然在實際的使用中，常因操作或運送過程中遭遇劇烈的機械衝擊如掉落衝擊而產生破壞。由於錫球除了提供晶片與印刷電路板之間電性訊號的路徑外，同時也提供封裝體結構上的支撐，因此錫球的信賴性是必須的考量。在動態荷載可靠度測試中，掉落衝擊測試為評估上板電子封裝體在製程、包裝、運送及日常使用狀態中，電路板受動態荷載劇烈彎曲之下，銲錫接點的可靠度。在現行掉落衝擊測試規範中，由電子工程設計發展聯合協會（Joint Electron Device Engineering Council, JEDEC）所制定的規範：JESD22-B110 與JESD22-B111已逐漸成為標準。JEDEC掉落衝擊測試可歸類為衝擊波控制（pulse-controlled）型式，其荷載為半正弦加速度衝擊波。
本文以晶圓級構裝為研究對象，藉由建構之全域模型/局部模型有限元素分析程序可求解上板電子封裝承受掉落衝擊荷載之暫態結構反應，同時涵蓋幾何非線性以及銲錫接點的彈塑性行為。其分析程序以精細之全域模型加以驗證，然後探討不同簡化全域模型對局部模型解的影響性並分析局部模型的收斂性。隨後，再進一步分析聚亞醯胺厚度對掉落衝擊測試信賴性及配合最佳化設計，以晶圓級構裝為測試物件，在錫球接點承受JEDEC掉落測試條件B(加速度1500G, 衝擊歷程0.5ms)下，將掉落測試信賴性予最佳化。為求得晶圓級構裝最佳掉落測試信賴性的設計，本文探討封裝的關鍵銲錫接點在不同控制因子條件下對正向應力及塑性應變影響。這些因子包含二層聚亞醯胺厚度，銲錫接點成份及晶片厚度，並利用田口方法，在L9直交表九組實驗設計中，找出封裝最佳化設計，再以實際掉落測試驗證最佳化設計且得到相同之結果。由結果可知，對晶圓級構裝結構的掉落測試信賴性而言，錫球成分為影響較大之控制因子，且較厚之第一層聚亞醯胺厚度會降低銲錫接點撥離應力與塑性應變。
其次，本文推導無阻尼單自由度結構系統承受半正弦加速度衝擊波荷載之暫態結構反應解析解，並以所得之最大反應比包絡線探討此類衝擊波控制型式掉落衝擊測試條件對印刷電路板暫態結構反應的影響。同時，延伸此研究，將阻尼效應導入結構系統中，推導出一含阻尼單自由度結構系統承受一半正弦加速度衝擊波的解析解，經實際應用於分析132 x 77 x 1 mm JEDEC 標準掉落測試板在承受不同JEDEC掉落測試條件下的反應頻譜，由結果可知當測試條件之G0值越小時，最大模態響應會趨近於靜態響應。對於測試條件C， B及H，第一模態並非具最大響應之模態。同時亦可知當測試條件之G0值增加時，更多模態的最大模態響應會發生在自由振動期間。接著以模態疊加法分析含15顆晶圓級構裝之 JEDEC 印刷電路測試板承受加速度度衝擊波的暫態結構反應，且與經由時間積分法分析之結果作比較。由結果可知，當結構系統銲錫接點材料特性均為線彈性，及整體結構無大變形效應，銲錫接點最大應力響應發生於測試板上Unit 3 或是Unit 13的位置，但結構系統之銲錫接點材料特性包含彈塑行為，及整體結構有大變形效應，銲錫接點最大應力響應發生於測試板上Unit 8的位置。

Lately, lead free solder is widely used in electronic products and the interconnection between the electronic components and printing circuit board due to the raising of environment protection consciousness. Comparing with the traditional lead contained solder, the material behavior of lead free solder is harder and more brittle. These characteristics make the interconnections easy to crack especially under the dynamic loading so as to force electronic products to challenge higher reliability under the dynamic loading. For the industry of electronic package, the package life of electronic products is deemed as the essential consideration in the operation period. In practice, electronic products are usually damaged due to a harsh mechanical impact such as drop impact during transportation or operation. The solder interconnections provide not only the electronic path between electric components and printing circuit board, but also the mechanical support of components on the printing circuit board so that the reliability of solder interconnection becomes an essential consideration for a package. Among those dynamic reliability tests, drop impact test is conducted to evaluate the solder interconnection reliability of package mounted on the printing circuit board when the printing circuit board is impacted by a harsh dynamic loading and hence results in a rush flexible bending during the processes of manufacturing, packaging and transportation or under regular operation of electronic products. In present, JESD22-B110 and JESD22-B111 defined by Joint Electron Device Engineering Council (JEDEC) have gradually become the key standards of drop impact tests in the electronic industry, in which the JEDEC drop impact test can be categorized as the pulse-controlled type with the applied loading of half-sine acceleration impact pulse.
The Wafer Level Chip Scale Package (WLCSP) is adopted in this study, By building the procedure of sub-modeling analysis comprised of geometry large deformation effect and solder interconnection material elastic-plastic behavior, the transient responses of board level electronic components subject to a drop impact loading can be obtained. Such a procedure can be verified by a detail global model, and the effects of various simplified global models on the sub-model as well as the convergence of the local model are analyzed. Accordingly, the effect of polyimide layer with different thickness on the reliability of the solder interconnection under a drop test is discussed, then an optimization process is applied to the WLCSP package in which the solder interconnection is subjected to a JEDEC drop impact test with Condition B (Peak Acceleration 1500G, duration 0.5ms) so as to obtain the optimization design of WLCSP drop impact reliability. To support such an optimization process, the effects of the critical solder interconnection with different control factors on the peeling stress and the plastic strain are analyzed. A Taguchi L9 orthogonal array is arranged for the optimization of three control factors, polyimide passivation layers, solder alloys and thickness of die to obtain the optimization design from 9 experiments. Subsequently, the JEDEC drop test is conducted to verify the optimization design with a coincident result. As a result, it is found that the solder alloy composition is the most important control factor for the reliability of WLCSP in the drop test as well as the thicker first polyimide layer is always facilitated to degrade the peel normal stress and the plastic deformation of solder joints.
Furthermore, the closed-form solutions for the transient structural responses of an undamped structural system with single degree of freedom subjected to an impact acceleration pulse of a half-sine waveform are derived. The largest response spectra is then applied to analyze the effect of different drop impact test conditions on the transient structural responses of the printed circuit board for the control of the impact acceleration pulse. Likewise, this study is extended to introduce the damped effect into the structural system so as to derive the closed-form solutions for transient structural responses of a damped structural system with single degree of freedom subjected to an impact acceleration pulse of a half-sine waveform. Such solutions are applied to analyze the response spectra of a JEDEC standard drop test board of 132 x 77 x 1 mm subject to various JEDEC drop conditions is demonstrated. The results show that the modal responses close to the static responses as the peak acceleration becomes smaller, and for Conditions C、B and H, the first modal does not have the maximum modal response as well as more modals will have their maximum modal responses during the free vibration stage. Accordingly, the transient responses of a JEDEC standard drop test board mounted with 15 ICs subjected to an impact acceleration pulse are calculated by the modal superposition method and the result is compared with that obtained by the time integration method. The results show that the maximum stress response is located at the outmost solder joint of Unit 3 or Unit 13 of the test board when the solder is elastic and there is no large deformation in the structure. On the other hand, the maximum stress response is located at the outmost solder joint of Unit8 of the test board when the solder is elastic-plastic there is large deformation in the structure.

中文摘要…………………………………………………………I
英文摘要…………………………………………………………IV
誌謝………………………………………………………………VIII
目錄………………………………………………………………IX
表目錄……………………………………………………………XII
圖目錄……………………………………………………………XIV
符號說明…………………………………………………………XXIII
第一章 緒論……………………………………………………1
1-1 前言……………………………………………………1
1-2 掉落測試簡介…………………………………………3
1-3 研究動機與目的………………………………………17
1-4 文獻回顧………………………………………………17
1-5 研究方法………………………………………………31
1-6 章節提要………………………………………………32
第二章 理論基礎………………………………………………33
2-1 研究主題………………………………………………33
2-2 支承激振法理論………………………………………34
2-3 全域模型局部模型暫態分析理論與流程……………39
2-4 半正弦衝擊波型式掉落衝擊測試反應頻譜分析理論
架構……………………………………………………41
第三章 全域模型局部模型之評估……………………………53
3-1 晶圓級構裝分析模型之建立與驗證…………………53
3-2 簡化全域之局部模型分析……………………………61
3-3 局部模型網格密度之影響……………………………75
3-4 局部模型方法之應用…………………………………82
第四章 以田口品質工程分析進行晶圓級構裝之最佳化設計
…………………………………………………………92
4-1 分析模型………………………………………………92
4-2 銲錫接點破壞指標……………………………………93
4-3 控制因子與水準………………………………………93
4-4 主實驗結果與探討……………………………………94
4-5 最佳化分析結果之驗證………………………………98
第五章 半正弦衝擊波型式掉落衝擊測試之反應頻譜分析與模態疊
加法之應用……………………………………………103
5-1 單自由度結構系統反應頻譜…………………………103
5-2 印刷電路板之反應頻譜………………………………108
5-3 JEDEC 上板級掉落測試之應用………………………115
5-4 掉落測試解析之探討…………………………………118
5-5 晶圓級構裝上板級掉落測試全模型分析……………125
第六章 結論與展望……………………………………………143
6-1 結論……………………………………………………143
6-2 未來研究方向…………………………………………148
參考文獻……………………………………………………………149
自述…………………………………………………………………157

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